83 lines
4.2 KiB
Markdown
83 lines
4.2 KiB
Markdown
# Hardware Capabilities
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## Interpretation Rule
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Blackwell-native means using target-specific scheduling, state ownership, or
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data movement supported by the target. Compiling the SM89 algorithm for
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`sm_121a` is not sufficient. SM100, SM120, and SM121 are separate schedules.
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## Capability Matrix
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| Capability | SM100 / B200 | SM120 / RTX PRO 6000 | SM121 / GB10 |
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| --- | --- | --- | --- |
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| Compute capability | 10.0 | 12.0 | 12.1 |
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| TMA global/shared tensor copies | Documented | Documented | Documented |
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| Native matrix programming model | `tcgen05.mma` with TMEM | warp-level `mma.sync` | SM120-family warp-level `mma.sync` |
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| Programmer-visible TMEM | Yes | Not exposed | Not exposed |
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| Native UMMA/tcgen05 INT8 | Exposed | Not exposed | Not exposed |
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| Sage-compatible INT8 path | `tcgen05.kind::i8` can be investigated | supported classic INT8 `mma.sync` | supported classic INT8 `mma.sync` |
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| FP8 PV path | `tcgen05` FP8 forms | warp-level FP8 `mma.sync` | warp-level FP8 `mma.sync` |
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| Hopper WGMMA | Not a portable target path | Not a target path | CUDA 13 rejects for `sm_121a` |
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| Registers per SM / max per thread | 64K / 255 | 64K / 255 | 64K / 255 |
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| Shared memory per SM / block | 228 / 227 KiB | 100 / 99 KiB | 100 / 99 KiB |
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| Maximum resident warps | 64 | 48 | 48 |
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| Maximum resident threads | 2048 | 1536 | 1536 |
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The public SM120/121 Blackwell MMA interface does not expose a Sage2-compatible
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UMMA INT8 QK operation. Exact SM121 work therefore retains the supported INT8
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`mma.sync` arithmetic while making TMA staging, role scheduling, ownership, and
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handoff Blackwell-specific. FP8/FP4 QK would define `vortex_fast`, not
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`vortex_exact`.
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## SM121 Facts From Retained Evidence
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- The current 128-thread kernel uses 255 registers/thread and 32 KiB dynamic
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shared memory.
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- Two CTAs provide eight resident warps, approximately `16.67%` of the 48-warp
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ceiling.
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- A 168-register cap reaches three CTAs but spills catastrophically; compiler
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lifetime cleanup is not enough.
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- CUDA 13 rejects `wgmma.fence`, `wgmma.mma_async`, `wgmma.commit_group`, and
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`wgmma.wait_group` for `sm_121a`.
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- CUTLASS 4.6 executes SM120-family block-scaled narrow MMA on GB10, but that is
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not an exact replacement for Sage2 INT8 QK.
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- TMA producer/consumer scheduling is available, but role-specific register
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redistribution, named-barrier cost, and concurrent INT8/FP8 issue must be
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measured rather than assumed.
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## Required Capability Probes Before Prototype
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1. Compile empty 256- and 320-thread role-specialized CTAs; record per-thread
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registers, aggregate register allocation, occupancy, and spill traffic.
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2. Test whether any supported register-allocation control can give producer and
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consumer warps different practical budgets on SM121.
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3. Measure one-CTA residency at 48, 52, 56, 64, and 68 KiB shared memory.
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4. Measure TMA plus named-barrier two-slot handoff for 4 and 8 KiB payloads.
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5. Verify simultaneous INT8 QK and FP8 PV warps produce actual overlap in pipe
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counters, not merely alternating aggregate utilization.
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6. Establish thread-block cluster/DSM support, placement, simultaneous
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residency, and remote shared-memory latency on GB10 before accepting VEA-C.
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7. Record sustained clocks and power behavior for 128-, 256-, and 320-thread
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CTAs.
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## Portability Policy
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- SM121 is first and must compile specifically for `sm_121a`.
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- SM120 may share API and contract code, but requires its own geometry,
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resource model, profiler evidence, and acceptance gates.
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- SM100 should use a separate `tcgen05`/TMEM design. Porting the SM121 register
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accumulator schedule unchanged would discard the principal SM100 capability.
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## Sources
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- NVIDIA CUDA GPU Compute Capability: https://developer.nvidia.com/cuda-gpus
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- CUDA Programming Guide: https://docs.nvidia.com/cuda/cuda-programming-guide/
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- PTX ISA: https://docs.nvidia.com/cuda/parallel-thread-execution/
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- CUTLASS Blackwell functionality:
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https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/blackwell_functionality.md
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- CUTLASS `mma_sm100_umma.hpp`, `mma_sm120.hpp`, and architecture config.
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- Local measurements: `SAGE2_BLACKWELL_DESIGN.md` and retained P0/post-FC2 NCU
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reports.
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Documented API support does not establish throughput, latency, queue depth, or
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bit identity. Those remain target-specific measurements.
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