Hardware Capabilities

Interpretation Rule

Blackwell-native means using target-specific scheduling, state ownership, or data movement supported by the target. Compiling the SM89 algorithm for sm_121a is not sufficient. SM100, SM120, and SM121 are separate schedules.

Capability Matrix

Capability	SM100 / B200	SM120 / RTX PRO 6000	SM121 / GB10
Compute capability	10.0	12.0	12.1
TMA global/shared tensor copies	Documented	Documented	Documented
Native matrix programming model	`tcgen05.mma` with TMEM	warp-level `mma.sync`	SM120-family warp-level `mma.sync`
Programmer-visible TMEM	Yes	Not exposed	Not exposed
Native UMMA/tcgen05 INT8	Exposed	Not exposed	Not exposed
Sage-compatible INT8 path	`tcgen05.kind::i8` can be investigated	supported classic INT8 `mma.sync`	supported classic INT8 `mma.sync`
FP8 PV path	`tcgen05` FP8 forms	warp-level FP8 `mma.sync`	warp-level FP8 `mma.sync`
Hopper WGMMA	Not a portable target path	Not a target path	CUDA 13 rejects for `sm_121a`
Registers per SM / max per thread	64K / 255	64K / 255	64K / 255
Shared memory per SM / block	228 / 227 KiB	100 / 99 KiB	100 / 99 KiB
Maximum resident warps	64	48	48
Maximum resident threads	2048	1536	1536

The public SM120/121 Blackwell MMA interface does not expose a Sage2-compatible UMMA INT8 QK operation. Exact SM121 work therefore retains the supported INT8 mma.sync arithmetic while making TMA staging, role scheduling, ownership, and handoff Blackwell-specific. FP8/FP4 QK would define vortex_fast, not vortex_exact.

SM121 Facts From Retained Evidence

The current 128-thread kernel uses 255 registers/thread and 32 KiB dynamic shared memory.
Two CTAs provide eight resident warps, approximately 16.67% of the 48-warp ceiling.
A 168-register cap reaches three CTAs but spills catastrophically; compiler lifetime cleanup is not enough.
CUDA 13 rejects wgmma.fence, wgmma.mma_async, wgmma.commit_group, and wgmma.wait_group for sm_121a.
CUTLASS 4.6 executes SM120-family block-scaled narrow MMA on GB10, but that is not an exact replacement for Sage2 INT8 QK.
TMA producer/consumer scheduling is available, but role-specific register redistribution, named-barrier cost, and concurrent INT8/FP8 issue must be measured rather than assumed.

Required Capability Probes Before Prototype

Compile empty 256- and 320-thread role-specialized CTAs; record per-thread registers, aggregate register allocation, occupancy, and spill traffic.
Test whether any supported register-allocation control can give producer and consumer warps different practical budgets on SM121.
Measure one-CTA residency at 48, 52, 56, 64, and 68 KiB shared memory.
Measure TMA plus named-barrier two-slot handoff for 4 and 8 KiB payloads.
Verify simultaneous INT8 QK and FP8 PV warps produce actual overlap in pipe counters, not merely alternating aggregate utilization.
Establish thread-block cluster/DSM support, placement, simultaneous residency, and remote shared-memory latency on GB10 before accepting VEA-C.
Record sustained clocks and power behavior for 128-, 256-, and 320-thread CTAs.

Portability Policy

SM121 is first and must compile specifically for sm_121a.
SM120 may share API and contract code, but requires its own geometry, resource model, profiler evidence, and acceptance gates.
SM100 should use a separate tcgen05/TMEM design. Porting the SM121 register accumulator schedule unchanged would discard the principal SM100 capability.

Sources

NVIDIA CUDA GPU Compute Capability: https://developer.nvidia.com/cuda-gpus
CUDA Programming Guide: https://docs.nvidia.com/cuda/cuda-programming-guide/
PTX ISA: https://docs.nvidia.com/cuda/parallel-thread-execution/
CUTLASS Blackwell functionality: https://github.com/NVIDIA/cutlass/blob/main/media/docs/cpp/blackwell_functionality.md
CUTLASS mma_sm100_umma.hpp, mma_sm120.hpp, and architecture config.
Local measurements: SAGE2_BLACKWELL_DESIGN.md and retained P0/post-FC2 NCU reports.

Documented API support does not establish throughput, latency, queue depth, or bit identity. Those remain target-specific measurements.

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