{
  "device": "NVIDIA GB10",
  "workload": "real H3 block 24, 37810 tokens, 56 heads, head dimension 128",
  "parity": {
    "manual_preparation_and_mainloop_vs_public_sage2_equal": true,
    "max_abs": 0.0,
    "mean_abs": 0.0
  },
  "uninstrumented_phase_medians_ms": {
    "k_mean_and_smoothing": 2.365136,
    "q_int8_quantization": 3.799392,
    "k_int8_subtract_mean_quantization": 3.825936,
    "v_transpose_pad_permute": 5.081152,
    "v_scale_fp8_quantization": 5.531616,
    "fused_mainloop": 237.089394
  },
  "ncu_mainloop": {
    "profiler_perturbed_duration_ms": 258.918464,
    "registers_per_thread": 255,
    "dynamic_shared_memory_bytes_per_cta": 32768,
    "threads_per_cta": 128,
    "grid_ctas": 16576,
    "theoretical_occupancy_percent": 16.67,
    "achieved_occupancy_percent": 16.83,
    "active_warps_per_sm": 8.08,
    "compute_throughput_percent": 75.54,
    "memory_throughput_percent": 31.61,
    "tensor_int_elapsed_cycles_percent": 37.77,
    "tensor_fp_elapsed_cycles_percent": 37.77,
    "fma_elapsed_cycles_percent": 15.01,
    "alu_elapsed_cycles_percent": 8.81,
    "scheduler_cycles_no_eligible_warp_percent": 63.53,
    "eligible_warps_per_scheduler": 0.46,
    "issued_warps_per_scheduler": 0.36,
    "warp_cycles_per_issued_instruction": 5.48,
    "warp_stall_cycles_per_instruction": {
      "wait_fixed_latency_dependency": 2.01,
      "math_pipe_throttle": 1.24,
      "not_selected": 0.26,
      "short_scoreboard": 0.25,
      "barrier": 0.19,
      "dispatch": 0.16,
      "long_scoreboard": 0.13,
      "mio_throttle": 0.12
    },
    "l2_request_sectors": 5046921579,
    "l2_request_bytes": 161501490528,
    "l2_hit_rate_percent": 98.84,
    "l2_miss_sectors": 57882308,
    "off_chip_request_proxy_bytes": 1852233856,
    "shared_wavefronts": 8161078676,
    "excess_shared_wavefronts": 626970624,
    "excess_shared_wavefront_percent": 7.68,
    "local_spilling_requests": 1458688
  },
  "tail_study_ms": {
    "q_37760_aligned": 239.229565,
    "q_37761_one_row_tail": 239.632672,
    "q_37810_real_tail": 239.999844,
    "kv_37760_aligned": 239.823065,
    "kv_37761_one_row_tail": 240.594522,
    "kv_37810_real_tail": 240.623859
  },
  "diagnosis": [
    "The mainloop is compute/scheduler limited, not off-chip-bandwidth limited.",
    "INT8 QK and FP8 PV each consume 37.77% of elapsed tensor-pipe capacity; their sum explains the 75.54% aggregate tensor activity.",
    "The 255-register footprint limits occupancy to two CTAs and eight warps per SM, leaving no eligible warp in 63.53% of scheduler cycles.",
    "Fixed-latency dependencies and tensor math-pipe throttling dominate stalls; global-memory scoreboards are secondary.",
    "Tail CTAs add less than 1 ms and are not the primary optimization target.",
    "Shared-memory bank conflicts add 7.68% excessive wavefronts and are the safest secondary target after scheduling/register experiments."
  ]
}