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CURRENT_STATE.md
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@ -1,6 +1,6 @@
# H3 Runtime Current State
Status date: 2026-08-26
Status date: 2026-08-22
This document is the canonical snapshot of implemented scope and remaining work.
Historical handoffs in `PLAN.md` and `PARITY.md` may describe older states.
@ -13,9 +13,7 @@ Historical handoffs in `PLAN.md` and `PARITY.md` may describe older states.
- Qwen text and vision conditioning, token refinement, video VAE encoding, H3
packed denoising, beta/RES sampling, video/audio decoding, and final MP4 mux.
- Resident HTTP runtime with warmup, readiness reporting, request-level backend
selection, timing stages, canonical-benchmark-only per-step CUDA timings,
peak sampling memory and latent checksums, FC2 dispatch deltas, optional
latent saving, and diagnostics.
selection, timing stages, optional latent saving, and diagnostic intermediates.
- SageAttention2 as the default quality backend.
- SDPA, forced cuDNN SDPA, FlashAttention-4, Sage3, Comfy Kitchen INT8, KJ Sage,
head-sliced, and Sol-Attn experimental backends.
@ -28,10 +26,6 @@ Historical handoffs in `PLAN.md` and `PARITY.md` may describe older states.
- Ragged Ulysses sequence parallelism with 2/4/6/8-rank transport tests.
- Sequence-sharded 50-block execution and distributed final projection.
- True H3 NVFP4 tensor parallelism for attention QKV/output and MLP FC1/FC2.
- Bit-exact fused H3 modulation and residual gates on GB10: `3.0%` faster over
the canonical 12-step 1344x768/124-frame sampling run with identical video
and audio checksums, `3.6-3.9%` faster individual blocks, approximately 390
MiB lower peak allocated memory, and 32 passing deployed tests.
- Automatic visible-GPU launchers and 1/2/4/6/8 benchmark matrix tooling.
- Real-checkpoint one-rank Ulysses-versus-TP identity at 864x480, 141 frames,
and 12 steps, including exact video and audio latent equality.
@ -72,272 +66,7 @@ Historical handoffs in `PLAN.md` and `PARITY.md` may describe older states.
- H3-specific attention backend optimized for real GB10 tensor shapes.
- Blackwell-native CUTLASS/CuTe or cuBLASLt NVFP4 GEMMs.
- CUDA graph capture and shape buckets.
The four-GEMM roofline study and canonical FC2 cuBLASLt integration are complete.
Remaining owned-GEMM work concerns QKV, attention output, and FC1 only and must
be justified against the post-FC2 profile.
The active NVFP4 fusion profile is now measured on one canonical GB10 block:
32 of 53 launches belong to the four scale/pack/GEMM paths. Native packed data,
block scales, and linear outputs are exact at every H3 projection width after
generalizing the block-scale swizzle. The next implementation must remove
intermediate traffic across these exact boundaries rather than deploy the
standalone packer, which is not consistently faster than Comfy Kitchen.
The active subcomponent is direct QKV projection into Sage2's required layout,
followed by direct attention output into the NVFP4 output projection's
token-major layout. The existing `scaled_mm_nvfp4` wrapper exposes only a
contiguous BF16 output, so true copy elimination requires either a supported
strided epilogue from its underlying CUTLASS kernel or an owned projection
collective. A post-GEMM copy kernel is useful only as a diagnostic and does not
satisfy this boundary-removal target. For single-GPU Sage2, the supported
strided NHD interface made that post-GEMM kernel unnecessary: Q/K/V remain
strided views of the interleaved projection output and Sage emits contiguous
token-major-compatible NHD output. The bit-exact path reduces canonical sampling
from `301.05 s` to `290.23 s` and is enabled for Spark deployments with
`H3_SAGE_QKV_LAYOUT=strided_nhd`.
NVFP4 streaming feasibility is confirmed but not yet deployable. Comfy Kitchen's
cuBLAS interface requires complete activation and scale pointers, while CUTLASS
DSL 4.6.2 runs block-scaled FP4 on SM121 and accepts the same logical H3 data.
The experimental alpha-before-BF16 epilogue is bit-exact for QKV, attention
output, and FC1 on 128-row real tiles. FC2 still differs because its reference
uses a different reduction policy, so no streamed producer is enabled.
The explicit implementation policy is to retain FC2 on cuBLAS and develop the
streamed CuTe path only for QKV, attention output, and FC1. This is a numerical
fallback, not a silent compatibility path: FC2's reference reduction order is
part of the exactness contract.
The fixed 128-row P1 producer-consumer checkpoint is complete. The existing
32-thread DMA warp now produces four BF16 activation rows per lane directly into
the owned GEMM's staged E2M1 A and E4M3 SFA shared-memory layouts. B/SFB remain
on TMA, and their completion publishes the stage to the unchanged MMA consumer.
No complete global activation QDATA or SFA tensor is passed to the streamed
kernel. Every real 128-K tile and the complete BF16 GEMM output are bit-exact for
QKV, attention output, and FC1. Matching Comfy requires its `--use_fast_math`
`rcp.approx.ftz.f32` encode-scale operation. FC2 streaming is explicitly
rejected and retains the cuBLAS fallback. The prototype is validator-only and
still needs canonical M/padding support and runtime packaging.
See `benchmarks/gb10-cute-p1-stream-a-summary.json`.
The first timing gate rejects direct per-CTA streaming. For 128 rows, the exact
streamed kernel is `9.14-12.98x` slower than the complete Vortex-scale plus
Comfy-pack/GEMM reference because every output-N CTA rereads and repacks A.
Measured producer cost is approximately `0.56-0.60 us` per `(N,K)` tile, and
break-even would require reusing A across 28-102 N tiles. Duplicating that many
accumulators is not viable. The active design is now a bounded global packed-tile
ring or persistent work queue that produces each `(M,K)` tile once, shares it
across N consumers, and recycles the slot without materializing the complete
activation. See `benchmarks/gb10-cute-p1-stream-a-timing-summary.json`.
The bounded-ring implementation uses caller-owned native QDATA/SFA buffers and
an allocation-free `_into` producer. A capacity sweep with one full-activation
scale selected 2048 rows: 6.19 MB for QKV/FC1 and 8.26 MB for attention output.
At that capacity, complete 37,810-row projection parity is exact for QKV,
attention output, and FC1 in blocks 0, 24, and 49, including the final 946-row
chunk. The subsequent single-model alternating gate rejects runtime QKV dispatch:
all three block outputs are bit-exact, but median block time regresses by `0.52%`
to `0.81%`. QKV capacity checks at 3072, 4096, 8192, and 37888 rows also fail to
produce a block-level gain; 4096 is closest at `0.24%` slower. Attention output
and FC1 remain experimental, and FC2 remains on Comfy/cuBLAS. Do not run
trajectory validation or enable the backend until launch fusion or a different
persistent scheduler passes this block gate. See
`benchmarks/gb10-cute-qkv-runtime-block-gate-summary.json`.
The historical pre-FC2 post-optimization canonical run was `288.93 s` with unchanged video
and audio checksums. Block 24 is `468.22 ms` median, of which production NHD
Sage2 attention consumes `258.47 ms`. Internal attribution places `238.81 ms`
in the SM89 attention mainloop, versus `7.68 ms` Q/K quantization and `10.65 ms`
V quantization. The deployed SM121 path therefore still spends most of the
block in an Ada-style MMA kernel. Recompiling SageAttention's Hopper WGMMA
mainloop for SM121 is not possible: CUDA 13 ptxas rejects WGMMA instructions for
`sm_121a`. CUTLASS SM120/121 UMMA supports F8/F6/F4, not the INT8 QK operation
required for exact Sage2 parity, so a native exact attention rewrite is paused.
The next practical boundary was the two approximately 10.5 ms AdaLN modulation
passes. Their exact BF16 values now feed NVFP4 scale/pack for QKV and FC1 without
materializing the modulated values, while retaining the current Comfy GEMMs.
The producer is byte-exact for complete block 0, 24, and 49 inputs. Integrated
block medians improve by `0.28-0.79%`; warmed two-step and canonical 12-step
trajectories improve by `0.52%` and `0.56%`, respectively, with bit-identical
video and audio tensors. Spark enables the path with
`H3_NVFP4_MODULATE_FUSION=1`. See `NVFP4_MODULATE_FUSION_DESIGN.md`,
`SAGE2_BLACKWELL_DESIGN.md`, and
`benchmarks/gb10-post-optimization-profile-summary.json`.
The FC2 cuBLASLt scheduling study and guarded canonical-shape integration are
complete. The production
heuristic's `_stream_k` kernel requests the same `25.664 GB` of operands as the
retained public split-K-1 schedule, but its L2 hit rate is only `53.32%` versus
`91.10%`; it incurs `9.853 GB` more L2 read misses and spends heavily in
synchronization polling. Algorithm 70, tile 20, stages 37, split-K 1 is
byte-exact with zero workspace. It improves complete blocks 0, 24, and 49 by
`8.16-8.88%`, the two-step trajectory by `7.50%`, and the canonical 12-step
trajectory from `278.201 s` to `255.371 s` (`8.21%`) with exact video and audio
latents. The final hardened production method improves 20-round blocks by
`7.86-9.36%` and the canonical 12-step trajectory from `286.431 s` to
`262.979 s` (`8.19%`), with 600 successful dispatches, zero fallback, and exact
latents. `H3_NVFP4_FC2_LT_SPLITK1=1` enables only the validated `M=37,810`
descriptor; nearby row counts can differ by two BF16 elements and therefore
retain the existing Comfy fallback. The extension and measured runtime ABI are
prepared during H3 model loading rather than on the first canonical request.
The resident service has now passed post-FC2 deployment and repeated canonical
baseline validation and is active on Spark at port `8001`. See
`research/fc2_nvfp4_scheduling/RESULTS.md`.
The Spark hot runtime was rebuilt and recreated with image
`sha256:5f879c43374bcedb89745971d7d95d82afc8fcf9c41d30f11b257c2863b9fe28`.
Health and startup warmup pass with modulation fusion enabled. A resident real
generation smoke completed in `2.14 s` (`0.227 s` sampling) and produced a valid
22-frame 320x192 H.264 file. The first startup warmup includes one-time CUDA
extension compilation. See
`benchmarks/gb10-nvfp4-modulate-fusion-deployment-smoke.json`.
Exact SwiGLU-to-FC2 NVFP4 producer fusion is also complete. It preserves the
two reference BF16 boundaries, emits byte-identical tensor scale/QDATA/SFA, and
retains the exact Comfy FC2 GEMM. Blocks 0, 24, and 49 improve by `2.14-2.26%`.
The warmed canonical 12-step run improves from `289.14 s` to `277.36 s`
(`4.07%`) with bit-identical video and audio tensors. Spark enables it with
`H3_NVFP4_SWIGLU_FUSION=1`. See `NVFP4_SWIGLU_FUSION_DESIGN.md` and
`benchmarks/gb10-nvfp4-swiglu-fusion-summary.json`.
Optional BF16 materialization inside both fused producers was tested for active
Turbo LoRA requests. The isolated canonical Turbo-4 trajectory was bit-exact,
but regressed from `131.11 s` to `135.14 s` (`3.08%`), so the prototype was
rejected. Active LoRA retains the exact materialized fallback instead of using
either producer fusion. See
`benchmarks/gb10-nvfp4-lora-producer-fusion-turbo4-isolated.json`.
The authoritative profile image is
`sha256:a15d0c09dd8cc82aaf2b564d3da760ea5ab8dec974f73075f7d30ac3a504815c`.
The active production overlay is
`sha256:6d880d628334c981c3d155bf5244e65e26e22cc9273c80145f646eee3c3698c2`;
it inherits the profiled binary/ABI layers and makes telemetry
canonical-benchmark-only. Production flags enable both accepted producers and
`H3_NVFP4_FC2_LT_SPLITK1=1`; ordinary requests do not create step events or
copy latents for checksums. `/ready`, startup warmup, repeated exact canonical
generation, profiler captures, and 58 tests pass.
A previous pre-FC2 fully fused Nsight recapture superseded the old approximately
515 ms block profile. Block 24 is `458.78 ms` median uninstrumented and
`465.78 ms` across the Nsight GPU span, with 41 kernels and only `0.084 ms` of
inter-kernel idle time. Sage2 is `57.60%` of kernel time, the four NVFP4 GEMMs
are `26.87%`, packing is `8.92%`, norm/RoPE is `4.27%`, and the two remaining
gate/add kernels are `2.35%`. A complete warmed step takes `23.708 s` and shows
the same distribution. Hardware counters attribute `56.25%` of the warm-cache
off-chip request proxy to the NVFP4 GEMMs even though Sage2 remains the time
bottleneck. See `benchmarks/gb10-fully-fused-fresh-nsight-summary.json`.
The authoritative post-FC2 resident baseline is now the median of three warmed,
unprofiled canonical runs: `256.464`, `255.447`, and `255.135 s`, giving
`255.447 s`. Every run produced the established video SHA-256
`c62d23a42972eab907ba42f93c50247ff17a9c454b4a53fe93d2e34f9fefe578` and audio
SHA-256 `852005383770480a6503504e1ffec86dd1fb63a69c6400f92da18e39e0986de2`,
with 600/600 FC2 dispatches and zero fallback. Peak sampling allocation and
reservation were `44,445,830,144` and `48,708,452,352` bytes.
The same-script generic block-24 decomposition control is `427.410 ms`; it
bypasses guarded FC2 and is not production-FC2 timing. A complete warmed step
has a `20.907 s` Nsight GPU span, `20.895 s` kernel time, 2,744 kernels,
`11.519 ms` total launch gaps, and `99.98%` launch-API/GPU overlap. The new time
ranking is Sage2 `62.36%`, NVFP4 GEMMs `19.95%`, packing `9.70%`, norm/RoPE
`5.19%`, and gate/add `2.63%`. Sage2 is therefore the next-ranked investigation,
but no new optimization has begun. See
`benchmarks/gb10-post-fc2-production-profile-summary-20260826.json`.
The real block-24 Sage2 scheduler study and exact SM89 P0 retune are complete.
Manual preparation plus the
unchanged prequantized SM89 mainloop is byte-exact against public SageAttention
2.2.0. Uninstrumented medians are `2.37 ms` for K mean/smoothing, `3.80 ms` for
Q quantization, `3.83 ms` for K subtract-mean quantization, `5.08 ms` for V
transpose/pad/permute, `5.53 ms` for V scale/FP8 quantization, and `237.09 ms`
for the fused mainloop. Nsight Compute reports 255 registers/thread, 32 KiB
dynamic shared memory/CTA, `16.83%` achieved occupancy, and no eligible warp in
`63.53%` of scheduler cycles. INT8 QK and FP8 PV each use `37.77%` of elapsed
tensor-pipe capacity; combined tensor activity is `75.54%`. The kernel is
scheduler/compute limited rather than off-chip-bandwidth limited: L2 hit rate is
`98.84%`, while fixed-latency dependency and math-pipe stalls dominate. Tail
CTAs add less than 1 ms.
The P0 mapped the exact register cliff: caps from 255 through 170 registers
remain at two CTAs and `16.67%` theoretical occupancy; only 168 registers reaches
three CTAs and `25%`, while generating `4.95 billion` local spill requests and
worsening no-eligible cycles to `78.79%`. Narrowed scopes reduced static spills
from 44/44 to 12/12 bytes and dynamic spill requests from `1.46 million` to
`0.40 million`, but changed interleaved latency by only `+0.06%` and worsened
no-eligible cycles. In-place score reuse, early K prefetch, and independent
softmax-chain interleaving were also byte-exact and neutral or slower.
The `7.68%` shared excess maps entirely to repeated V-staging `LDGSTS.128`
instructions. Padding V to a 128-byte shared stride increased shared memory to
40 KiB but left all `626,970,624` excessive wavefronts unchanged and changed
latency by `-0.04%`. No variant crossed the 3% complete-block gate, so none was
integrated or deployed. See
`benchmarks/gb10-sage2-p0-register-scheduler-analysis.json` and the associated
P0 latency JSON and NCU reports.
The exact Sage2 entry-fusion P1 is also complete and rejected. A single CUDA
kernel fused strided-NHD Q/K RMSNorm, split-half RoPE, and Sage2 Q INT8
quantization while leaving K mean/quantization, V preparation, and the SM89
mainloop unchanged. Randomized edge lengths and canonical block 0/24/49 tensors
were bit-exact through prepared Q/K, Q/K quantization, scales, K mean, Sage2
output, and complete block output. Entry-only median latency improved by
`20.9-23.4%`, but canonical complete-block median improvement was only `0.73%`,
`0.86%`, and `0.53%` for blocks 0, 24, and 49. The candidate removed one launch
(`87` to `86`), did not change peak memory, and reduced complete-block L2 traffic
by only `0.136-0.155%`. It therefore failed the required 1% gate; the opt-in
runtime branch was removed and two-step/12-step validation was skipped. See
`benchmarks/gb10-sage2-p1-entry-fusion-analysis.json` and its referenced parity,
timing, and Nsight reports.
The exact Sage2 V-preparation P2 is complete and rejected at its isolated gate.
An owned three-stage CUDA path consumes projection-strided NHD BF16 V and emits
Sage2's padded/permuted E4M3 V plus FP32 per-channel scales without materializing
the approximately 517 MiB BF16 transpose tensor. FP8 bytes and scales are exact
for 13 boundary lengths from 1 through 37,810 tokens with 56 heads. On the
canonical shape, median V preparation improves from `10.56 ms` to `6.39 ms`
(`39.48%`), but the `4.17 ms` absolute saving projects to only `0.91%` of the
`458.78 ms` complete block and misses the required `6.0 ms` isolated go gate.
Complete-block and trajectory validation were therefore skipped, and production
dispatch remains unchanged. See
`benchmarks/gb10-sage2-p2-vprep-analysis.json`.
The exact Sage2 mainloop P3 temporal-pair experiment is also complete and
rejected. Two warp pairs alternated QK/online-softmax and prior-tile PV while
retaining private per-warp scores, softmax state, and output accumulators. The
isolated extension is sanitizer-clean and byte-exact over 13 adversarial short
shapes plus the real 37,810-token block-24 SHA. In a 50-sample alternating run,
mainloop median changed from `245.44 ms` to `245.20 ms`, only `0.10%`, and
missed the absolute `<220 ms` gate. Ptxas reports 254 registers/thread and
32/24-byte static store/load spills versus baseline 255 registers and 24/24-byte
spills. NCU, block integration, and trajectory validation were skipped.
Production remains unchanged. See
`benchmarks/gb10-sage2-p3-temporal-pair-analysis.json` and
`research/sage2_temporal_pair/`.
Vortex Exact Attention is initialized as an isolated clean-sheet research
project under `research/vortex_exact_attention/`. Phase 0 imports and verifies
the retained SageAttention 2.2.0 exactness contract at commit
`d1a57a546c3d395b1ffcbeecc66d81db76f3b4b5`; it does not repeat P0-P3 or alter
dispatch. Ten retained oracle artifacts match their recorded SHA-256 values.
Phase 1 selects the VEA-B Q128 paired-owner architecture: four QK/softmax warps
own `RS/RS_f8/m/d`, four separate PV warps own `RO`, and two producer warps own
K/V staging. Its `180-207 ms` mainloop range is a heuristic screen, not achieved.
Phase 2A capability probes now pass with CUDA block-scope mbarriers: 96
registers/thread for handoff, 139 for synthetic combined ownership, zero spills,
one ten-warp CTA/SM, `0.076800 ms` barrier-only p50, and concurrent INT8/FP8
progress in 48/48 blocks. Canonical Q/K/V/output fixtures are captured and
reload-verified against the locked Sage2 output hash. The inline named-barrier
primitive is rejected on racecheck. One isolated aligned-shape prototype is
authorized; no attention kernel or attention speedup exists. Production remains
Sage2.
The four-GEMM roofline selected FC2, and the guarded public split-K-1 schedule
closed that target. Fresh NCU values at block 24 are `26.38 ms` QKV, `8.48 ms`
attention output, `36.17 ms` FC1, and `16.20 ms` FC2. Sage2 remains much larger:
its NCU-replayed mainloop is `259.00 ms`, with 255 registers/thread, `16.65%`
achieved occupancy, `98.85%` L2 hit rate, and `161.50 GB` L2 requests. No new
kernel work starts until this ranking is accepted.
- Fused Q/K RMSNorm, RoPE, and layout work on the Sage2 quality path.
## Quality Work Remaining
@ -379,20 +108,13 @@ kernel work starts until this ranking is accepted.
## Recommended Execution Order
1. Treat the post-FC2 profile as the GB10 baseline; investigate Sage2 only under
a separately approved experiment with exactness and absolute latency gates.
2. Capture matched SM120 and SM100 component profiles and package Sage2 on SM120.
3. Resume NVFP4 GEMM/epilogue work only with a design that preserves the
accepted producer fusions and exact BF16 boundaries.
4. Validate full quoted-dialogue video lip-sync and close the audio prompt change.
5. Add explicit task schemas and automated single-GPU mode tests.
6. Implement full Ref2VA, including reference-audio encoding.
7. Add CUDA graph buckets after the kernel and shape policies stabilize.
8. Harden the service API and operational deployment.
9. Complete RunPod NCCL validation and distributed scaling benchmarks.
See `PERFORMANCE_ROADMAP.md` for measured component costs, architecture-specific
targets, quality gates, and the rationale for this ordering.
1. Validate full quoted-dialogue video lip-sync and close the audio prompt change.
2. Correct the inactive fused Sol path.
3. Add explicit task schemas and automated single-GPU mode tests.
4. Implement full Ref2VA, including reference-audio encoding.
5. Build the H3-specific attention backend and CUDA graph buckets.
6. Harden the service API and operational deployment.
7. Complete RunPod NCCL validation and distributed scaling benchmarks.
The current single-GPU T2VA/FL2VA runtime is mature. Distributed execution is
implemented and CPU/one-GPU validated, with real multi-GPU NCCL results still

47
DISTRIBUTED.md
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@ -93,46 +93,6 @@ replace multi-GPU NCCL parity testing.
## RunPod
### Regional volume bootstrap
Prepare the same benchmark assets in any RunPod data center with one guarded
command. The tool creates or reuses a network volume, attaches it to a temporary
two-vCPU pod, downloads the two pinned Hugging Face artifacts, verifies their
SHA-256 hashes, uploads a `git archive` of the current commit, writes a manifest,
and terminates the CPU pod in a `finally` block.
Set credentials in the process environment; do not pass secrets on the command
line or commit them:
```powershell
$env:RUNPOD_API_KEY = "..."
$env:HF_TOKEN = "..."
python .\tools\prepare_runpod_region.py --region US-MO-2 --dry-run
python .\tools\prepare_runpod_region.py --region US-MO-2 `
--volume-name h3-vortex-us-mo2 --yes
```
Resume an interrupted preparation without creating another volume:
```powershell
python .\tools\prepare_runpod_region.py --region US-MO-2 `
--volume-id VOLUME_ID --yes
```
Matching files are skipped by checksum. Partial `aria2` downloads resume in
place. The resulting volume contains:
- `ComfyUI/models/diffusion_models/minimax_h3_fl2va_pruned_nvfp4.safetensors`
- `ComfyUI/models/text_encoders/qwen3vl_32b_minimax_h3_nvfp4_awq.safetensors`
- `h3-runtime/h3-blackwell-runtime-<commit>.tar.gz`
- `h3-runtime/regional-bootstrap-manifest.json`
- `h3-runtime/artifacts-ready`
The archive intentionally contains committed files only. The manifest records a
dirty-worktree flag so an operator can see when local uncommitted changes were
excluded. CPU compute is automatically terminated on success, failure, or
Ctrl+C; the network volume is retained for GPU pods.
The target is one eight-GPU RTX PRO 6000 Blackwell machine. Query current stock
using the guarded API v2 client:
@ -189,13 +149,6 @@ and NCCL 2.27.7 selected `P2P/CUMEM` with GDR enabled and zero NVLS channels.
RunPod allocations varied between cross-NUMA `SYS` and same-NUMA `NODE`
topologies, so topology must be recorded with every scaling result.
One B200 in US-NC-2 completed the same 1344x768 SDPA tensor benchmarks in
`79.72s` at 124 frames and `257.86s` at 243 frames. Relative to one RTX PRO
6000, these are `1.23x` and `1.21x` speedups, but sampling cost is `2.64x` and
`2.69x` higher at the measured `$6.79/hour` B200 rate. The full timings,
checksums, memory peaks, and comparison are in
`benchmarks/b200-vs-rtxpro6000-server-sdpa-1344x768-seed440420.json`.
## Remaining GPU Gates
- Real NCCL identity at 4, 6, and 8 GPUs; two-GPU transport is complete.

14
Dockerfile.postprofile
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@ -1,14 +0,0 @@
FROM h3-blackwell-runtime:post-fc2-profiled-a29b896
WORKDIR /opt/h3-blackwell-runtime
# Preserve the profiled binary/ABI layers while making benchmark diagnostics opt-in.
COPY src/h3_blackwell_runtime/runtime.py src/h3_blackwell_runtime/runtime.py
COPY src/h3_blackwell_runtime/sampler.py src/h3_blackwell_runtime/sampler.py
COPY tools/serve_hot_runtime.py tools/serve_hot_runtime.py
COPY tools/benchmark_hot_runtime.py tools/benchmark_hot_runtime.py
COPY tools/profile_sampling_stages.py tools/profile_sampling_stages.py
COPY tools/summarize_nsys_profile.py tools/summarize_nsys_profile.py
COPY tools/summarize_ncu_profile.py tools/summarize_ncu_profile.py
COPY tools/build_post_fc2_profile_summary.py tools/build_post_fc2_profile_summary.py
COPY tests/test_turbo.py tests/test_turbo.py

4
Dockerfile.spark
View file

@ -31,10 +31,6 @@ RUN git clone https://github.com/Saganaki22/ComfyUI-sol-attn.git /opt/ComfyUI-so
RUN python -m pip install --no-cache-dir --no-deps -e . \
&& python -c "import comfy_kitchen, torch; from sageattn3 import sageattn3_blackwell; assert hasattr(torch.ops.comfy_kitchen, 'rms_rope_split_half_'); assert hasattr(comfy_kitchen, 'int8_attention'); assert hasattr(comfy_kitchen, 'int8_attention_is_available'); print(torch.__version__, torch.version.cuda)"
ENV TORCH_EXTENSIONS_DIR=/opt/h3-blackwell-runtime/.torch_extensions
RUN TORCH_CUDA_ARCH_LIST=12.1 python -c \
"from h3_blackwell_runtime.nvfp4_quant import _vortex_scale_extension; from h3_blackwell_runtime.fc2_lt import _fc2_lt_extension; print(_vortex_scale_extension().__file__, _fc2_lt_extension().__file__)"
ENV H3_MODEL_PATH=/models/minimax_h3_ref2va_pruned_nvfp4.safetensors
ENV PYTHONPATH=/opt/ComfyUI-sol-attn
ENV TORCH_COMPILE_DISABLE=0 TORCHDYNAMO_DISABLE=0

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# NVFP4 Modulation Producer Fusion
## Target
Fuse the two per-block AdaLN modulation operations into the exact NVFP4
activation scale and packing producer for attention QKV and MLP FC1. Retain the
current Comfy Kitchen GEMMs and all BF16 numerical boundaries.
At the canonical 37,810-token shape, block 24 spends a median 10.47 ms on MSA
modulation and 10.60 ms on MLP modulation. Production already mutates the two
RMSNorm outputs in place, so this fusion targets memory traffic rather than a
separate allocation.
## Dataflow
Current:
1. Read normalized BF16 input and write modulated BF16 output.
2. Read modulated output to compute the global NVFP4 activation scale.
3. Read modulated output again to produce packed E2M1 data and E4M3 scales.
4. Execute the unchanged Comfy NVFP4 GEMM.
Prototype:
1. Read normalized input, reproduce the reference modulation BF16 boundary, and
reduce its absolute maximum without materializing the modulated tensor.
2. Read normalized input again, reproduce the same BF16 values, and write exact
QDATA/SFA directly into caller-owned buffers.
3. Execute the unchanged Comfy NVFP4 GEMM.
## Exactness Contract
- Preserve segment-specific shift and scale selection.
- Preserve `(x * (scale + 1)) + shift` operation order and BF16 rounding.
- Preserve Vortex's approximate-reciprocal NVFP4 encoding behavior.
- Produce byte-identical QDATA and E4M3 block scales.
- Produce bit-identical QKV/FC1 outputs before changing block dispatch.
## Gate
1. Adversarial modulation and quantization tests.
2. Exact packed bytes and linear outputs for blocks 0, 24, and 49.
3. Alternating module-forward benchmark in one loaded block.
4. Full 50-block step and two-step trajectory only after all three blocks gain.
5. Canonical 12-step trajectory before enabling the path by default.
## Result
The producer is byte-exact for complete 37,810-row block 0, 24, and 49 inputs.
It takes 6.02 ms for block 24 QKV input. Integrated block medians improve by
0.28-0.79%, a warmed two-step trajectory improves by 0.52%, and the warmed
canonical 12-step run improves from 285.996 s to 284.408 s (0.56%). Video and
audio tensors are bit-identical. Spark deployments enable the path with
`H3_NVFP4_MODULATE_FUSION=1`.

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# NVFP4 Streaming Design
## Decision
Comfy Kitchen 0.2.31 cannot consume incrementally produced NVFP4 tiles. Its
Python path allocates complete activation QDATA, complete swizzled block scales,
and a complete BF16 output before calling `cublas_gemm_blockwise_fp4` with fixed
full-tensor pointers. The registered operator has no tile callback, producer
interface, output stride, user output, or custom epilogue argument.
True activation-materialization removal therefore requires an owned CUTLASS or
CuTe DSL mainloop. Wrapping `scaled_mm_nvfp4` cannot provide it.
## Available Foundation
The Spark image contains:
- CUDA 13.0.88.
- NVIDIA CUTLASS DSL 4.6.2.
- CUDA Python bindings.
- Working SM121 block-scaled E2M1/E4M3 MMA support.
The official CUTLASS 4.6 SM120/SM121 persistent cooperative block-scaled GEMM
was compiled and executed on GB10 with E2M1 A/B, E4M3 scales, FP32 accumulation,
and BF16 output. A 1024x1024x1024 case passed its reference check at `16.9664 us`
and approximately `126.57 TFLOP/s`.
The public kernel still takes complete global A, B, SFA, and SFB tensors and
uses separate TMA descriptors for all four. CUTLASS does not expose a ready
BF16-to-NVFP4 input producer callback.
## Numerical Constraint
H3's activation quantization uses:
1. One exact global BF16 absolute maximum.
2. One FP32 tensor scale derived from that maximum.
3. One E4M3 block scale per 16 activation values.
4. E2M1 values quantized using both scales.
No activation tile can be packed reference-exactly until the full activation's
global reduction is complete. The minimum exact design therefore has two
phases:
1. Reduce the complete BF16 activation to one FP32 scale.
2. Produce packed tiles and consume them in block-scaled MMA.
A future cooperative mega-kernel could combine the phases around a grid-wide
barrier, but that is not the first prototype. Programmatic dependent launch can
overlap independent weight preparation but cannot transfer shared-memory tiles
between kernels.
## Reuse Constraint
The SM121 block-scaled kernel uses cluster shape `1x1x1`; there is no TMA
multicast path for sharing one packed activation tile among output-N CTAs.
Replacing global packed A with an ordinary per-CTA software producer would make
every output-N CTA reread BF16 A and repeat scale/pack work. BF16 A is materially
larger than packed E2M1 plus E4M3 scales, so this can lose despite removing the
initial packed-tensor write.
The owned kernel must therefore test an N-group schedule where one CTA retains
one or more packed A K-tiles while accumulating multiple output-N tiles. The
number of simultaneous N tiles is constrained by accumulator registers and
shared memory. This reuse factor is a first-class tuning parameter.
## Prototype Sequence
### P0: Owned Prepacked Baseline
Port the official persistent cooperative SM120/SM121 CuTe DSL kernel behind an
experimental Vortex entry point. Match Comfy Kitchen for the four H3 projection
shapes using existing packed activation and weight tensors.
Acceptance:
- Exact BF16 output versus `scaled_mm_nvfp4`.
- H3 widths 5376, 7168, and 14336 plus QKV output width 21504.
- No regression beyond measurement noise before changing the A producer.
Current P0 result: real 128-row H3 tiles execute through the CuTe kernel. Raw
block-scaled BF16 output is bit-exact for QKV, attention output, and FC1. P0 is
not complete:
- The experimental epilogue now applies H3's FP32 global-scale product before
BF16 conversion. QKV, attention output, and FC1 are bit-exact.
- FC2 at K=14336 differs even before global scaling (`max_abs=8192`, mean
`0.015625`). The correct alpha epilogue reduces final error to mean
`2.42e-5`, but bit equality still fails with `max_abs=16`. Its cuBLAS path
uses a different reduction/Stream-K policy; CUTLASS K tiles 128 and 256
produce the same non-reference result.
- The stock CuTe Float32 output mode fails the official example's own GB10
reference check and cannot be used as an accumulation oracle.
Do not begin P1 until the FC2 reduction contract is exact or FC2 is deliberately
kept on the existing cuBLAS fallback. See
`benchmarks/gb10-cute-p0-h3-summary.json`.
Decision: FC2 remains explicitly on the existing cuBLAS path. P1 and later
streaming work target QKV, attention output, and FC1 only. This preserves the
reference FC2 Stream-K reduction order and therefore full-model bit parity while
the owned producer-consumer path is developed independently.
### P1: Single-Tile Software A Producer
Replace the A and SFA TMA loads for one fixed output tile with a software warp
that loads BF16 A, generates E4M3 scales and E2M1 values into the existing staged
shared-memory layouts, and commits a producer-consumer pipeline stage. Keep
prepacked B/SFB and the existing MMA consumer and BF16 epilogue.
Acceptance:
- Packed bits and scale bytes agree with Comfy for every consumed tile.
- GEMM output is bit-exact for adversarial and randomized tile inputs.
- No global QDATA or SFA allocation in the captured kernel.
Current P1 checkpoint: the fixed 128-row producer-consumer path is exact. The
existing 32-thread DMA warp loads four BF16 rows per lane, writes E2M1 and E4M3
directly into the staged `sA`/`sSFA` layouts, and lets retained B/SFB TMA
completion publish each stage to the unchanged MMA consumer. The kernel takes
BF16 A and one tensor scale; it does not take or allocate global activation
QDATA or SFA.
Every 128-K tile has zero differing packed or scale bytes for real QKV,
attention-output, and FC1 activations. Their complete 128-row GEMM outputs are
also bit-exact after the alpha-before-BF16 epilogue. Exact Comfy compatibility
requires PTX `rcp.approx.ftz.f32`, because Comfy Kitchen builds the quantizer
with `--use_fast_math`; ordinary FP32 division changes E2M1 decisions at
midpoints. CUTLASS DSL 4.6.2 also requires a static contiguous view for vector
FP4 stores, as lowering the same store through a rank-2 dynamic layout aborts
MLIR construction. Evidence is in
`benchmarks/gb10-cute-p1-stream-a-summary.json`.
P1 is not deployment-complete. The next work is canonical row-count and padding
support and an owned runtime module rather than validator-time patching of the
CUTLASS example. FC2 continues to reject streaming and remains on Comfy/cuBLAS.
### P2: N-Group Reuse
Accumulate multiple output-N tiles per produced A tile. Sweep N-group size and
mainloop stages while recording registers, occupancy, achieved tensor
throughput, BF16 bytes read, and total projection latency.
Reject the no-materialization design if repeated BF16 reads or reduced occupancy
make it slower than the prepacked baseline. In that case, test a bounded global
ring buffer of packed tiles as the producer-consumer compromise.
Current P2 result: reject the one-producer-per-output-N-CTA schedule. At 128
rows, streamed execution is `9.14x`, `12.98x`, and `12.44x` slower than the
complete scale+pack+GEMM reference for QKV, attention output, and FC1. Producer
overhead scales at approximately `0.56-0.60 us` per `(N tile, K tile)`. Merely
matching the removed activation quantization cost would require theoretical N
reuse factors of 78, 28, and 102 respectively. Those factors are not practical
through duplicate accumulator state, especially with the existing 232-register
consumer requirement.
The next prototype is therefore a bounded global packed-tile ring or persistent
work queue: produce each `(M,K)` A tile once, let all required N consumers reuse
it, then recycle the slot. This deliberately restores bounded packed global
traffic while avoiding complete activation materialization. See
`benchmarks/gb10-cute-p1-stream-a-timing-summary.json`.
The bounded-ring capacity sweep is complete. A caller-owned `_into` CUDA
producer writes exact QDATA and SFA into reusable buffers, and one full-activation
scale is reused by every chunk. Capacities 128, 512, 1024, 2048, and 4096 were
measured; 2048 rows is the selected point. It uses 6.19 MB for QKV/FC1 and 8.26
MB for attention output. Smaller chunks leave launch overhead, while 4096 rows
regresses.
At 2048 rows, measured chunk latency improves by `10.7%` for QKV, `14.4%` for
attention output, and `11.3%` for FC1. Modeled canonical totals improve by
`10.1-12.5%` after charging one full-activation scale reduction. All packed
bytes, scale bytes, and BF16 outputs are exact. QKV, attention output, and FC1
therefore advance to complete real-projection validation; FC2 remains on
Comfy/cuBLAS. See `benchmarks/gb10-cute-p2-ring-capacity-summary.json`.
Complete 37,810-row projection parity now passes for QKV, attention output, and
FC1 in blocks 0, 24, and 49. All 19 chunks, including the final 946-row chunk,
are bit-exact with equal full checksums. QKV has a stable approximately 32 ms
ring time and improves in every tested block, so it advances to opt-in resident
runtime validation. Attention output timing is mixed. FC1 timing is unstable
under duplicate-model unified-memory pressure, including one container stop,
despite exact outputs. Do not approve those two roles from this harness. See
`benchmarks/gb10-cute-p2-ring-full-projection-summary.json`.
The opt-in QKV-only integration passes numerical validation but fails the
single-model performance gate. Alternating baseline/ring calls in one loaded
block are bit-exact for blocks 0, 24, and 49, while the 2048-row schedule is
`0.52-0.81%` slower at block level. Capacity checks from 3072 through a full
37888-row workspace do not recover a gain; 4096 rows is closest at `0.24%`
slower. The reusable output also requires serialized model requests because the
next projection reuses its storage after GPU work is enqueued. Keep this backend
disabled. The next valid prototype must fuse chunk launches through a persistent
work queue or replace the scheduler before repeating this block gate; trajectory
validation is intentionally skipped. See
`benchmarks/gb10-cute-qkv-runtime-block-gate-summary.json`.
### P3: Full H3 Projection
Support canonical H3 M/N/K shapes, padding, current weight/block-scale layout,
and token-row slicing. Integrate through `Nvfp4Linear` behind an opt-in feature
flag.
### P4: Exact Epilogue
After the owned GEMM is exact, add the explicit BF16 conversion, gate multiply,
residual add, and final BF16 rounding sequence. Validate this independently from
input streaming.
## Validation Ladder
Every phase must pass, in order:
1. Adversarial scale, E4M3, E2M1, signed-zero, midpoint, NaN, and infinity cases.
2. Randomized packed-tile and GEMM comparisons.
3. Real QKV, output, FC1, and FC2 projections at blocks 0, 24, and 49.
4. Complete block equality.
5. All 50 blocks in a denoiser step.
6. Two-step video/audio trajectory equality.
7. Canonical 12-step video/audio checksum equality.
8. Full block Nsight recapture and peak-memory comparison.
No streamed path becomes a deployment default before all applicable exactness
gates pass.

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# NVFP4 SwiGLU Producer Fusion
## Implementation
The H3 MLP now recomputes its exact BF16 SwiGLU values inside the Vortex global
scale and NVFP4 pack passes instead of materializing the 37,810x14,336 BF16
activation. The FC2 Comfy Kitchen NVFP4 GEMM and its reduction order are
unchanged.
The fused producer preserves both BF16 boundaries:
1. `silu(gate)` rounded to BF16.
2. The BF16 SiLU result multiplied by BF16 `up` and rounded to BF16.
It then preserves the established Vortex tensor-scale compatibility cast,
E4M3 block scales, E2M1 encoding, approximate reciprocal, and Comfy physical
scale layout.
## Validation
- Randomized BF16 tensor scale, QDATA, and SFA are byte-exact.
- Real block-24 FC1 output is byte-exact; producer median is 21.93 ms.
- Blocks 0, 24, and 49 are bit-exact and improve by 2.14-2.26%.
- Warmed two-step video/audio tensors are bit-exact.
- Warmed canonical 12-step tensors are bit-exact and improve from 289.14 s to
277.36 s, or 4.07%.
Spark single-GPU deployments enable the path with
`H3_NVFP4_SWIGLU_FUSION=1`. Active FC2 LoRA, full-precision, pre-scale,
autograd, and unsupported dtype/layout cases use the materialized fallback.

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# H3 Performance Roadmap
This document is the canonical performance plan for the direct MiniMax H3
runtime on GB10/SM121, RTX PRO 6000/SM120, and B200/SM100. It separates measured
results from projections and requires numerical and visual gates before an
approximate optimization becomes a default.
## Executive Decision
The first component, bit-exact H3 modulation and residual-gate fusion on GB10,
is complete.
This is the best first engineering target because:
1. The current path spends about `39 ms` per representative block in modulation
and residual gates, before counting the separate `25.8 ms` SwiGLU operation.
2. A Triton reference with explicit BF16 rounding already exists and has been
validated bit-exact against eager H3 block behavior.
3. The optimization does not alter attention semantics, weights, precision, or
scheduler behavior.
4. The same elementwise design applies to SM100, SM120, and SM121.
5. It provides a low-risk test of the profiling, fallback, parity, and deployment
machinery required by later custom kernels.
The accepted NVFP4 producer fusions and canonical FC2 public split-K-1 schedule
are complete. The authoritative post-FC2 profile ranks Sage2 first at `62.36%`
of warmed-step kernel time, followed by NVFP4 GEMMs at `19.95%` and packing at
`9.70%`. No follow-on optimization begins from this document alone; Sage2 is the
next investigation only after a separate exactness and absolute-latency plan.
Completed result: blocks 0, 24, and 49 are bit-exact and `3.6-3.9%` faster;
the canonical 12-step sampling run is checksum-identical and improves from
`310.11 s` to `301.05 s` (`3.0%`). Peak allocated memory falls by
`408,825,856` bytes. Evidence is in
`benchmarks/gb10-h3-fused-elementwise-1344x768-124f-seed440420.json`.
Internal closeout summary:
> Vortex Component 1 is complete. We implemented bit-exact H3 modulation and
> residual-gate fusion on GB10, reducing canonical 12-step sampling from 310.11
> seconds to 301.05 seconds while retaining identical video and audio checksums.
> The fused runtime improves individual transformer blocks by 3.6-3.9%, reduces
> peak allocated memory by approximately 390 MiB, and passes 32 deployed
> numerical and integration tests. This establishes that Vortex can remove
> meaningful H3 execution overhead without changing the model's numerical
> program or generated output.
This is measured engineering evidence, not a projected optimization.
## Historical GB10 Baseline
The representative workload is 1344x768, 124 frames, 100 synthetic refined-text
tokens, and 37,810 packed tokens. Measurements use block 24 unless noted.
Warmed top-level sampling step:
| Backend | Step time | Relative to Sage2 |
| --- | ---: | ---: |
| SageAttention 2.2.0 | `25.414 s` | baseline |
| Sol BF16, tau 1.3 | `21.573 s` | `1.18x` |
| Sol residual-INT8 Q/K, tau 1.3 | `19.774 s` | `1.29x` |
The denoiser consumes effectively all warmed-step time. Packing takes about
`15 ms`; output transformation and the RES update together take about `1.4 ms`.
Representative Sage2 block:
| Component | P50 | Approximate block share |
| --- | ---: | ---: |
| Attention | `259.9 ms` | `50.5%` |
| NVFP4 QKV/out/FC1/FC2 projections | `151.1 ms` | `29.3%` |
| Modulation, residual gates, and SwiGLU | `64.9 ms` | `12.6%` |
| QKV and output layout materialization | `20.3 ms` | `4.0%` |
| Norm and RoPE | `19.7 ms` | `3.8%` |
| Full module forward | `514.9 ms` | baseline |
SageAttention 2.2.0 internals:
| Component | P50 |
| --- | ---: |
| Q/K INT8 quantization | `6.45 ms` |
| V FP8 quantization | `10.19 ms` |
| Attention forward | `239.00 ms` |
| K smoothing and framework estimate | `2.98 ms` |
Sol residual-INT8 Q/K internals at tau 1.3 with exact conditioning KV:
| Component | P50 |
| --- | ---: |
| K summary and residual quantization | `4.45 ms` |
| V summary | `2.45 ms` |
| Q quantization and routing threshold | `4.27 ms` |
| Total preparation | `11.53 ms` |
| Routed forward estimate | `114.88 ms` |
| Total | `126.42 ms` |
INT8 P-by-V is not useful on GB10: it increases total Sol attention time to
`138.65 ms`.
## Authoritative Post-FC2 GB10 Baseline
The exact resident workload is 1344x768, 124 frames, 12 steps, seed `440420`,
Sage2, 100 synthetic refined-text tokens, and 37,810 packed tokens. After one
unmeasured canonical warmup, three unprofiled resident runs took `256.464`,
`255.447`, and `255.135 s`; the authoritative median is `255.447 s`. All three
runs dispatched FC2 600/600 times with zero fallback and matched the retained
video/audio SHA-256 values exactly. Peak allocated/reserved sampling memory was
`44.446/48.708 GB`.
Fresh block-24 and warmed-step evidence:
| Measurement | Post-FC2 result | Previous pre-FC2 result | Change |
| --- | ---: | ---: | ---: |
| Generic block decomposition control p50 | `427.410 ms` | `458.775 ms` | `-6.84%` |
| Warmed-step GPU span | `20.907 s` | `23.707 s` | `-11.81%` |
| Warmed-step kernel time | `20.895 s` | `23.694 s` | `-11.81%` |
| Kernel count | `2,744` | `2,694` | `+50` |
| Total positive launch gaps | `11.519 ms` | `12.995 ms` | `-11.36%` |
Post-FC2 warmed-step kernel ranking:
| Rank | Component | Time | Share |
| ---: | --- | ---: | ---: |
| 1 | Sage2 preparation and mainloop | `13.029 s` | `62.36%` |
| 2 | Four NVFP4 GEMMs | `4.168 s` | `19.95%` |
| 3 | NVFP4 scale and packing | `2.027 s` | `9.70%` |
| 4 | Norm and RoPE | `1.084 s` | `5.19%` |
| 5 | Residual gate/add | `0.549 s` | `2.63%` |
The profile is GPU-bound: summed kernel time is `99.94%` of the GPU span and
kernel-launch API intervals overlap GPU kernels by `99.98%`. CPU launch work is
not the next bottleneck. The block decomposition control calls generic NVFP4
linears and bypasses guarded FC2; production FC2 evidence comes from resident
NSYS and targeted NCU, not its `mlp_fc2` attribution.
## Quality Boundary
Current Sol routing is a performance bound, not an accepted Sage2 replacement.
| Sol policy | Relative L2 versus Sage2 | Performance |
| --- | ---: | ---: |
| Fully dense, tau -100 | `0.0171` | `3.2x` slower than Sage2 |
| Exact conditioning KV, tau 0.8 | about `0.471` | about `1.12x` faster |
| Exact conditioning KV, tau 1.3 | about `0.626` | about `1.87x` faster in isolated attention |
No measured Sol setting is both faster than Sage2 and numerically Sage-like.
Exact conditioning sinks protect prompt/audio rows but do not remove sparse
video-attention error. A timestep or block hybrid therefore needs complete
latent, audio, lip-sync, and visual evaluation; attention-output timing alone
cannot approve it.
## Opportunity Ranking
The recoverable ranges below overlap and must not be added directly.
| Priority | Target | Measured cost | Plausible saving | Risk | Portability |
| ---: | --- | ---: | ---: | --- | --- |
| Complete | Fuse modulation and residual gates | `39.1 ms/block` projected scope | `3.6-3.9%` measured block gain | Low | Validated on SM121 |
| Closed | Canonical FC2 public split-K-1 | `53.618 ms` baseline FC2 | `15.636 ms` accepted | Low | GB10 canonical shape only |
| 1 | Sage2 preparation and mainloop | `13.029 s/step`, `62.36%` | Not assigned | High | Separate SM100/120/121 policy |
| 2 | Remaining four NVFP4 GEMMs | `4.168 s/step`, `19.95%` | Not assigned | Medium | Architecture-specific |
| 3 | NVFP4 scale and packing | `2.027 s/step`, `9.70%` | Not assigned | Medium | SM100/120/121, retune launch |
| 4 | Norm and RoPE | `1.084 s/step`, `5.19%` | Not assigned | Medium | Shape-specific |
| 5 | CUDA graphs or persistent execution | `11.519 ms` measured launch gaps | Small | Medium | Shape-bucket-specific |
Native Sage NHD was tested and rejected as a standalone optimization. It was
numerically exact but did not materially improve median path time and had worse
tail latency. Eliminating layout cost requires fusion with QKV production,
RMSNorm/RoPE, or the attention kernel rather than changing Sage's layout flag.
## Implementation Phases
### Phase 1: Exact H3 Elementwise Fusion
Status: complete on GB10/SM121. Spark deployments enable
`H3_FUSED_ELEMENTWISE=1`; other deployments retain the eager default until
validated on their architecture.
Implement an opt-in direct-runtime path for:
1. RMSNorm output plus segmented AdaLN scale/shift modulation.
2. Attention residual gate/add.
3. MLP segmented scale/shift modulation.
4. MLP residual gate/add.
5. A request-layout segment-index cache reused by all 50 blocks and sampling
steps.
Preserve explicit BF16 rounding boundaries. Keep the eager implementation as a
fallback until all gates pass.
The achieved `3.0%` sampling gain is materially below the original theoretical
`20-35 ms/block` opportunity. Before extending this fusion, profile:
1. Which modulation, gate, or add launches remain outside the fused path.
2. Whether tensor conversions or intermediate allocations remain.
3. Whether the fused kernels are launch-bound or bandwidth-bound.
4. Whether generated kernels perform unnecessary loads or stores.
5. Which remaining elementwise operations can move into exact NVFP4 GEMM
epilogues.
The GB10 Nsight follow-up is complete. One warmed block has 53 kernel launches.
The fused path contains exactly two modulation and two residual gate/add
launches; no modulation, gate, or add launch remains outside it. Those four
kernels still consume about `20.48 ms`, showing that the residual is tensor
traffic rather than launch overhead. The four NVFP4 projections account for 32
launches across scale reduction/finalization, scalar conversions, block-scale
initialization, activation packing, and GEMM. Their current intermediate tensor
sizes sum to approximately `7.73 GB` per block when counted at each projection
boundary. See
`benchmarks/gb10-component2-nsys-summary-1344x768-124f-seed440420.json`.
Success criteria:
- Bit-exact outputs at blocks 0, 24, and 49.
- Bit-exact one-step full-denoiser video and audio outputs.
- No change to a complete 12-step latent checksum.
- At least `5%` median block improvement or `3%` warmed sampling improvement.
- No peak-memory regression.
### Phase 2: Architecture Baselines
Capture the same component report on each architecture before writing a shared
kernel abstraction:
| Architecture | Required baseline |
| --- | --- |
| SM121 GB10 | Sage2 2.2, current Vortex scale path, 38K and 74K tokens |
| SM120 RTX PRO 6000 | SDPA, packaged Sage2 2.2, 38K and 74K tokens |
| SM100 B200 | SDPA, forced cuDNN SDPA, Sage2 if supported, 38K and 74K tokens |
Record actual kernel names, clocks, power, SM utilization, achieved bandwidth,
and achieved tensor throughput. Do not infer one architecture's policy from
another's result.
### Phase 3: NVFP4 Fused Projection Prototype
Status: active on GB10/SM121; isolated FC2 library scheduling is complete and
awaits production integration.
The first profile also exposed and fixed a native activation-packer layout bug:
the previous width-specific block-scale swizzle failed at the attention output's
7168-feature width. The replacement general 128-row by 4-scale-column mapping is
packed-bit exact at H3 widths 5376, 7168, and 14336, and all four linear outputs
now match Comfy exactly. Standalone native packing is not consistently faster,
so it remains prototype infrastructure rather than a deployed backend.
Component 2 execution order, revised from the measured Nsight profile:
1. Make QKV projection land directly in the attention backend's required
layout, with Q/K normalization and RoPE operating there.
2. Make attention output land directly in the token-major layout consumed by
the output projection.
3. Eliminate complete NVFP4 packed-activation and block-scale materialization
through a CUTLASS/CuTe producer-consumer or persistent design.
4. Integrate reference-exact residual gates into output-projection and FC2
epilogues.
5. Optimize the standalone packer only after the boundary-removing paths exist.
6. Recapture the complete block profile after every accepted boundary removal.
The first two layout items are complete for single-GPU Sage2 on GB10. Sage2
accepts the projection-strided NHD Q/K/V views directly, including in-place Q/K
normalization and RoPE, and emits contiguous NHD output that reshapes to
token-major rows without a copy. This removes three QKV copies and the attention
output copy without replacing the projection GEMM. Blocks 0, 24, and 49 and the
two-step and canonical 12-step trajectories are bit-exact. Canonical sampling
improves from the Component 1 baseline of `301.05 s` to `290.23 s` (`3.6%`),
with cumulative improvement of `6.4%` from the original `310.11 s` baseline.
The accepted Nsight recapture falls from 53 to 49 launches and contains none of
the four large BF16 layout-copy kernels.
Evidence is in
`benchmarks/gb10-sage-strided-nhd-summary-1344x768-124f-seed440420.json`.
The target NVFP4 dataflow is not another wrapper around
`scaled_mm_nvfp4`. Tensor-core GEMMs require exact packed-data and block-scale
layouts, so avoiding durable HBM intermediates likely requires an owned
CUTLASS/CuTe collective with tile-level producer-consumer execution.
Interface investigation confirms this boundary. Comfy Kitchen 0.2.31 allocates
complete QDATA, block-scale, and BF16 output tensors before invoking a cuBLAS
blockwise FP4 GEMM with fixed pointers. It cannot consume incremental tiles.
CUTLASS DSL 4.6.2's stock SM121 E2M1/E4M3 persistent kernel passes on GB10, but
its public mainloop also TMA-loads prebuilt A and SFA. The owned implementation
will follow `NVFP4_STREAMING_DESIGN.md`: preserve the mandatory global-scale
reduction, replace the A/SFA producer in one fixed tile, then measure multi-N
reuse before attempting full H3 shapes.
P0 is complete for the selected streamed roles. The owned CuTe bridge and
alpha-before-BF16 epilogue are bit-exact
for QKV, attention output, and FC1, proving E2M1, E4M3, and global-scale
interoperability. FC2 remains non-exact because its reference uses a different
reduction policy (`max_abs=16` after the correct epilogue). Resolve that policy
or retain an explicit FC2 cuBLAS fallback before the streaming A producer begins.
FC2 fallback is selected. The streamed backend will reject FC2 dispatch and use
the existing Comfy/cuBLAS implementation there; QKV, attention output, and FC1
advance to the P1 software A/SFA producer.
The fixed 128-row P1 producer-consumer checkpoint is complete. The stock
kernel's 32-thread DMA warp produces four rows per lane directly into staged
E2M1 A and E4M3 SFA shared memory; only B and SFB retain TMA loads. Every 128-K
tile has zero packed-data and scale-byte differences for real QKV,
attention-output, and FC1 activations, and all three complete GEMM outputs are
bit-exact after the fused alpha epilogue. The streamed kernel receives BF16 A
plus its tensor scale and has no global activation QDATA or SFA input.
The final arithmetic contract includes Comfy's `--use_fast_math` behavior:
encode scale must use PTX `rcp.approx.ftz.f32`. Correctly rounded division changes
FP4 midpoint decisions for real H3 values. CUTLASS DSL 4.6.2 also requires a
static contiguous destination view for vector FP4 stores. Evidence is in
`benchmarks/gb10-cute-p1-stream-a-summary.json`.
The P1 timing gate rejects direct per-output-N-CTA streaming. At 128 rows, the
exact streamed kernel is `9.14x` slower than the complete reference projection
for QKV, `12.98x` slower for attention output, and `12.44x` slower for FC1.
Producer overhead is linear at approximately `0.56-0.60 us` per `(N,K)` tile.
Break-even against the removed quantizer would require theoretical N reuse of
78, 28, and 102 tiles respectively, which cannot be implemented by retaining
duplicate accumulator state under the current register budget.
The next P2 prototype is a bounded global packed-tile ring or persistent work
queue. It must produce each `(M,K)` A tile once, expose it to all N consumers,
and recycle the slot, trading bounded global packed traffic for elimination of
the measured repeated BF16 conversion. Do not add canonical-shape runtime
dispatch for the rejected schedule. FC2 remains an explicit Comfy/cuBLAS
fallback. Evidence is in
`benchmarks/gb10-cute-p1-stream-a-timing-summary.json`.
The bounded-ring P2 checkpoint now uses caller-owned native QDATA/SFA buffers and
an allocation-free `_into` producer. A capacity sweep with one full-activation
scale selected 2048 rows. The ring occupies 6.19 MB for QKV/FC1 and 8.26 MB for
attention output. Measured chunk latency improves QKV by `10.7%`, attention
output by `14.4%`, and FC1 by `11.3%`; modeled canonical totals improve by
`10.1-12.5%`. Every packed byte, scale byte, and BF16 output matches the
reference. The 4096-row point regresses, confirming that larger buffers are not
monotonically better. Evidence is in
`benchmarks/gb10-cute-p2-ring-capacity-summary.json`.
Complete 37,810-row projection parity now passes for QKV, attention output, and
FC1 in blocks 0, 24, and 49. Every one of the 19 chunks, including the final
946-row tail, is bit-exact. QKV has a stable approximately 32 ms ring time and a
positive result across all three blocks. Attention-output timing is mixed. FC1
timing is not usable from the duplicate-model harness because multi-gigabyte
output pressure caused large variance and one container stop.
The opt-in QKV runtime gate is complete and rejects the current bounded-ring
schedule. An alternating baseline/ring benchmark inside one loaded block removes
the clock, allocator, input, and model-copy bias present in separate-process
profiles. Blocks 0, 24, and 49 remain bit-exact, but the 2048-row ring regresses
median block time by `0.81%`, `0.52%`, and `0.52%`, respectively. On block 24,
3072 rows regress by `1.00%`, 4096 by `0.24%`, 8192 by `4.80%`, and a 37888-row
full workspace by `14.49%`. The isolated projection win does not survive the
chunk launch and scheduler overhead. Keep the implementation opt-in and disabled;
do not spend trajectory-validation compute until a launch-fused work queue or a
different persistent scheduler passes this same block gate. Attention output and
FC1 remain experimental, and FC2 remains the explicit Comfy/cuBLAS fallback.
Evidence is in `benchmarks/gb10-cute-qkv-runtime-block-gate-summary.json`.
The post-optimization profile identifies Sage2's mainloop as the largest cost.
Canonical sampling is `288.93 s`; block 24 is
`468.22 ms`, and its production NHD Sage2 call is `258.47 ms`. The existing
SM89 mainloop alone takes `238.81 ms`, while Q/K and V quantization together take
`18.34 ms`. A direct Hopper WGMMA retarget was rejected by SM121 ptxas, and
CUTLASS SM120/121 UMMA does not support the INT8 QK operation needed for exact
Sage2 parity. Do not substitute Sage3's different FP4 algorithm under the exact
optimization contract.
The next implementable exact target was AdaLN modulation into NVFP4 production.
The MSA and MLP modulation passes cost `10.47 ms` and `10.60 ms` and materialize
their values in the RMSNorm buffers solely for QKV and FC1. The deployed fusion
recomputes the exact BF16 values inside Vortex scale/pack and retains Comfy
GEMMs. Complete producer bytes match in blocks 0, 24, and 49. Alternating block
medians improve by `0.28-0.79%`; warmed two-step and 12-step runs improve by
`0.52%` and `0.56%`, with bit-identical outputs. Spark deployments enable
`H3_NVFP4_MODULATE_FUSION=1`. Evidence is in
`benchmarks/gb10-nvfp4-modulate-fusion-summary.json`.
SwiGLU-to-FC2 producer fusion is complete. Recomputing the exact BF16 SiLU and
multiply boundaries inside Vortex scale/pack removes the complete intermediate
activation while retaining the reference Comfy FC2 GEMM. The real producer is
byte-exact and takes `21.93 ms`. Alternating blocks 0, 24, and 49 improve by
`2.14-2.26%`; the warmed canonical 12-step trajectory improves by `4.07%` with
identical video and audio tensors. Enable `H3_NVFP4_SWIGLU_FUSION=1` for Spark
single-GPU deployments. Evidence is in
`benchmarks/gb10-nvfp4-swiglu-fusion-summary.json`.
The previous pre-FC2 post-fusion profile superseded the earlier approximately 515 ms
block distribution. With all production flags enabled, fresh block-24 timing is
`458.78 ms` median without Nsight and `465.78 ms` across the Nsight GPU span.
The 41 kernels have only `0.084 ms` total inter-kernel idle time, so CPU launch
gaps are not a block-level bottleneck. A complete warmed sampling step takes
`23.708 s`, contains 2,694 kernels, and has `12.995 ms` total inter-kernel idle
time.
The fresh block kernel-time distribution is:
| Component | Time | Share |
| --- | ---: | ---: |
| Sage2 preparation and mainloop | `268.22 ms` | `57.60%` |
| Four NVFP4 GEMMs | `125.11 ms` | `26.87%` |
| NVFP4 scale and packing | `41.53 ms` | `8.92%` |
| Norm and RoPE | `19.86 ms` | `4.27%` |
| Two residual gate/add kernels | `10.94 ms` | `2.35%` |
The one-step distribution independently matches these shares within 0.5
percentage points. The standalone modulation and SwiGLU kernels are gone.
Their remaining producer work is `13.04 ms` for modulated QKV/FC1 packing and
`23.04 ms` for SwiGLU-to-FC2 packing. The block still records 8,009,578,496
positive self-allocated bytes, but there are no large activation-layout copy
kernels or explicit CUDA memcpy operations. Remaining conversions are small
AdaLN table and scalar operations.
GB10 exposes no direct physical DRAM-byte counter. Nsight Compute measures
`320.999 GB` of L2-request traffic for the block. With cache control disabled,
L2 read/write miss sectors imply a `42.117 GB` off-chip request proxy: NVFP4
GEMMs account for `56.25%`, packing `18.25%`, Sage2 `15.09%`, norm/RoPE
`6.54%`, and gates `3.87%`. This separates the time bottleneck, Sage2, from the
off-chip traffic bottleneck, the NVFP4 GEMMs. Do not select a new kernel from
the old profile. See
`benchmarks/gb10-fully-fused-fresh-nsight-summary.json`.
The FC2 follow-up resolves that projection's `16.1x` off-chip amplification.
The production heuristic launches an undocumented-sentinel `_stream_k` kernel;
the retained documented configuration is cuBLASLt algorithm 70, tile 20,
stages 37, public split-K 1, reduction scheme 0, and zero workspace. Both
schedules request the same `25.664 GB` of operands, but split-K 1 raises L2 hit
rate from `53.32%` to `91.10%`, removes `9.853 GB` of L2 read misses, and raises
tensor-pipe activity from `25.01%` to `82.42%`. There is no material global
partial-accumulator or output-reduction traffic; the baseline instead spends
heavily in Stream-K synchronization polling and loses traversal locality.
The candidate is byte-exact and improves FC2 p50 from `53.618 ms` to
`15.636 ms`. Complete blocks 0, 24, and 49 improve by `8.16-8.88%`; two-step
and canonical 12-step trajectories improve by `7.50%` and `8.21%`, with exact
video and audio latents. The custom persistent-kernel branch is therefore
closed. Guarded production integration is complete behind
`H3_NVFP4_FC2_LT_SPLITK1=1`. Its direct 20-round block gate improves blocks
0/24/49 by `9.36%`, `8.16%`, and `7.86%`; the exact canonical 12-step gate
improves by `8.19%`
with 600 successful dispatches and zero fallback. Shape testing found two-BF16
differences at several nearby row counts, so only `M=37,810` is eligible and
all variable shapes retain Comfy. The post-FC2 baseline and profiling are now
complete, and a telemetry-opt-in overlay of the profiled binary image is
resident again. See
`research/fc2_nvfp4_scheduling/RESULTS.md` and
`benchmarks/gb10-fc2-nvfp4-library-sweep-20260825.json`.
The mandatory post-FC2 recapture now establishes the production baseline.
Three exact resident runs have a `255.447 s` median. Block 24 falls from the
previous `458.775 ms` to `427.410 ms`, while warmed-step GPU span falls from
`23.707 s` to `20.907 s`. Aggregate NVFP4 GEMM time falls `33.52%`; Sage2 now
occupies `62.36%` of kernel time. Targeted NCU confirms FC2 at `16.20 ms`,
`91.06%` L2 hit rate, `26.07 GB` requested L2 traffic, and `77.65%` memory
throughput. Sage2 remains the dominant exact target, but no implementation has
started. See `benchmarks/gb10-post-fc2-production-profile-summary-20260826.json`.
The follow-up real block-24 Sage2 decomposition now selects the next exact
kernel experiment. Manual preparation plus the existing prequantized mainloop
is byte-exact against public SageAttention 2.2.0. Uninstrumented median phase
times are `2.37 ms` K smoothing, `7.63 ms` combined Q/K quantization, `10.61 ms`
combined V transpose/quantization, and `237.09 ms` for the fused mainloop.
The full-counter mainloop capture is profiler-perturbed to `258.92 ms`, so its
duration is not used as the baseline. Its ratios establish the bottleneck:
| Mainloop metric | Result |
| --- | ---: |
| Registers per thread | `255` |
| Dynamic shared memory per CTA | `32 KiB` |
| Achieved occupancy | `16.83%` / `8.08` warps per SM |
| Scheduler cycles with no eligible warp | `63.53%` |
| INT8 QK tensor-pipe utilization | `37.77%` of elapsed cycles |
| FP8 PV tensor-pipe utilization | `37.77%` of elapsed cycles |
| Combined tensor-pipe utilization | `75.54%` |
| Memory throughput | `31.61%` |
| L2 hit rate | `98.84%` |
| L2 request traffic | `161.50 GB` |
| Off-chip request proxy | `1.85 GB` |
| Excess shared-memory wavefronts | `7.68%` |
This explains why high SM activity did not imply a saturated tensor pipeline.
QK and PV alternate on separate INT and FP tensor sub-pipelines, while online
softmax, scaling, conversion, and synchronization occupy scalar pipelines.
Only `0.46` warps per scheduler are eligible on average. Fixed-latency
dependencies consume `2.01` of the `5.48` cycles between issued instructions,
and math-pipe throttle consumes another `1.24`; memory scoreboards are much
smaller. The 255-register footprint limits the kernel to two CTAs per SM, so it
cannot hide these dependencies. Q and KV tail sweeps each add less than 1 ms and
exclude tail scheduling as the primary target.
The source-identical classic SM89 P0 is complete and rejected. The exact
three-CTA cliff is 168 registers/thread, not approximately 170: 170 still has
two CTAs and `16.67%` theoretical occupancy, while 168 reaches `25%` at the cost
of `4.95 billion` local spill requests and `78.79%` no-eligible cycles. Caps from
240 through 170 never change residency and progressively worsen scheduler
eligibility.
Byte-exact source variants also missed the 3% gate. Narrowed scopes reduced
static spills from 44/44 to 12/12 bytes and dynamic spill requests by `73%`, but
improved interleaved latency by only `0.06%`. In-place score storage was
`+0.01%`; early K prefetch was `-0.30%`; independent softmax-chain interleaving
was `-0.02%`. The persistent 128-register FP32 output fragment plus exact QK or
instantaneous PV fragments prevents a source-only lifetime cleanup from
reaching the next residency tier.
The shared-memory follow-up is also closed. Source attribution maps all
`626,970,624` excessive wavefronts to four repeated V-staging `LDGSTS.128`
instructions. A 128-byte padded V stride raised dynamic shared memory from 32
to 40 KiB but left the excess count exactly unchanged and changed latency by
`-0.04%`. No complete-block benchmark or deployment was run because no mainloop
variant crossed 3%. Evidence is in
`benchmarks/gb10-sage2-p0-register-scheduler-analysis.json`, the per-variant
latency JSON files, and the P0 NCU reports.
Vortex Exact Attention now owns the next exact-attention design investigation.
Phase 0 imports and verifies the retained Sage2 evidence rather than repeating
P0-P3. The exact contract, fixture hashes, proof limits, and prior-work exclusion
matrix are under `research/vortex_exact_attention/`. Phase 1 recommends VEA-B,
a Q128 ten-warp pipeline with permanent disjoint QK/softmax and PV/output owners.
Its `180-207 ms` mainloop and `205-235 ms` complete-attention ranges are
heuristic screening models, not measured results. Phase 2A capability probes
pass: selected block-scope mbarriers use 96 registers/thread and 51.2 KiB shared
memory, permit one ten-warp CTA/SM, report zero spills and sanitizer errors, and
measure `0.076800 ms` barrier-only p50 across 591 epochs. Synthetic INT8/FP8 role
clocks overlap in 48/48 blocks. Canonical fixtures are captured and byte-locked.
This authorizes only an isolated aligned-shape prototype; production dispatch
remains unchanged and no attention speedup is claimed.
Materializing the optional BF16 LoRA input while these fused producers pack
NVFP4 was also tested against the official Turbo-4 adapter. The isolated
1344x768, 124-frame trajectory was bit-exact but regressed from `131.11 s` to
`135.14 s` (`3.08%`). Reject this implementation: its extra BF16 writes cost
more than the removed standalone producer. Active LoRA must retain the existing
materialized fallback unless a future design consumes the producer values
without global-memory materialization. Evidence is in
`benchmarks/gb10-nvfp4-lora-producer-fusion-turbo4-isolated.json`.
An exact residual-gate epilogue must preserve this numerical program:
1. Complete NVFP4 GEMM accumulation.
2. Convert to the reference BF16 GEMM output.
3. Apply the reference-equivalent gate multiplication and its BF16 boundary.
4. Add the BF16 residual using the reference operation order.
5. Round the final output to BF16.
Bit-exact GEMM output alone is insufficient. Validate randomized epilogues,
representative real blocks, all 50 blocks in one denoiser step, a two-step
trajectory, and the canonical 12-step trajectory before enabling an epilogue.
The direct-layout target extends naturally to distributed execution: QKV tiles
must be able to land in rank-destined Ulysses buffers, and attention output must
land in the output projection's local token-major layout without an intervening
transpose or contiguous copy.
Prototype behind `Nvfp4Linear` so model code remains unchanged. Compare:
1. Comfy Kitchen baseline.
2. Vortex scale plus Comfy pack/GEMM.
3. Fused scale and activation pack.
4. Fused scale, pack, GEMM, bias, and output epilogue.
5. Transformer Engine or CUTLASS reference where supported.
Gate every variant on packed activation identity, linear output error, block
output error, full denoiser-step error, and final media quality.
### Phase 4: Dense Sage-Compatible Attention
The first owned attention kernel should remain dense and target Sage2 behavior:
1. Consume strided BSHD views directly from fused QKV output.
2. Preserve Sage2 per-warp INT8 Q/K quantization and FP8 V policy.
3. Preserve its accumulation and K-smoothing behavior.
4. Fuse Q/K/V preparation with the attention launch where profitable.
5. Emit token-major output suitable for the NVFP4 output projection without an
intermediate transpose/contiguous allocation.
6. Tune independently for SM100, SM120, and SM121.
The initial goal is `1.5x` attention speedup with bit-exact Sage2 output where
the operation order permits it; any nonzero tolerance must be declared and
quality-gated before implementation. A `2x` attention target is stretch.
### Phase 5: Sparse Hybrid Research
Only after the dense backend passes:
1. Keep early quality-sensitive sampling steps dense.
2. Keep first/last sensitive transformer blocks dense.
3. Force text, reference, and audio conditioning KV blocks exact.
4. Sweep tau by timestep using complete generated media, not random attention
tensors alone.
5. Reject any policy that degrades prompt adherence, identity, lip sync, audio
onset, or temporal stability.
## Performance Targets
### GB10 / SM121
The authoritative exact resident median is `255.447 s` for a warmed 12-step
1344x768/124-frame sampling run.
| Target | Estimated sampling | Speedup |
| --- | ---: | ---: |
| Conservative | `215-240 s` | `1.3-1.4x` |
| Engineering | `170-195 s` | `1.6-1.8x` |
| Stretch | `130-145 s` | `2.1-2.3x` |
| Aggressive ceiling | about `120 s` | about `2.5x` |
Use `1.5x` as the commitment target, `1.8x` as the engineering target, and
`2.3x` as stretch. Do not plan around a `5x` end-to-end gain.
### RTX PRO 6000 / SM120
These projections have lower confidence because the measured RTX baseline uses
PyTorch SDPA rather than packaged Sage2.
| Workload | Current SDPA | Engineering target | Stretch target |
| --- | ---: | ---: | ---: |
| 1344x768, 124 frames | `97.94 s` | `45-60 s` | `35-45 s` |
| 1344x768, 243 frames | `311.02 s` | `120-170 s` | `90-120 s` |
Packaging and profiling Sage2 2.2 on SM120 is the first RTX action. Expected
overall improvement is `1.6-2.2x` at 124 frames and `1.8-2.6x` at 243 frames;
stretch ranges are `2.2-2.8x` and `2.6-3.5x` respectively. These are planning
ranges, not commitments.
### B200 / SM100
Measured B200 SDPA sampling is `79.72 s` at 124 frames and `257.86 s` at 243
frames, only `1.23x` and `1.21x` faster than RTX PRO 6000 despite much larger
theoretical FP4 and memory-bandwidth capability. No optimized B200 target is
assigned until component profiling confirms actual SDPA dispatch, NVFP4 kernel
selection, clocks, power, utilization, and achieved throughput.
The current B200 result measures this runtime path, not B200's hardware ceiling.
## Evidence
- `benchmarks/gb10-sampling-component-profile-1344x768-124f-seed440420.json`
- `benchmarks/gb10-37810-token-optimization-profile-seed440420.json`
- `benchmarks/rtxpro6000-server-1v2-sdpa-scaling-seed440420.json`
- `benchmarks/b200-vs-rtxpro6000-server-sdpa-1344x768-seed440420.json`
- `benchmarks/gb10-post-fc2-resident-baseline-20260826.json`
- `benchmarks/gb10-post-fc2-production-profile-summary-20260826.json`
- `benchmarks/gb10-post-fc2-warmed-step-20260826.nsys-rep`
- `benchmarks/gb10-post-fc2-block24-targeted-20260826.ncu-rep`
- `tools/profile_h3_block.py`
- `tools/profile_attention_components.py`
- `tools/profile_hybrid_attention.py`
- `tools/profile_sampling_stages.py`
Component timings use synchronized probes for attribution. End-to-end claims
must use separate uninstrumented runs. Resident services remained loaded during
GB10 profiling, so medians are preferred over means and final claims require an
isolated rerun.

27
PLAN.md
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@ -93,33 +93,6 @@ Current NVFP4 activation quantization status:
- `vortex_native` BF16->NVFP4 pack is parity-safe for real H3 FC1/FC2 activation shapes, including qdata, cuBLAS tiled block-scale layout, signed zero, tie-to-even FP4 rounding, and downstream `scaled_mm_nvfp4` linear output.
- Keep Comfy Kitchen as the default production packer. Pack-only sweep `8d90cec` shows native 512-thread pack is essentially tied on FC1 (`1.090 ms` vs CK `1.098 ms`) but still slower on FC2 (`2.977 ms` vs CK `2.886 ms`). Use `vortex_native` only as an experimental benchmark path until the wide-FC2 pack kernel is redesigned.
Major cross-architecture performance opportunities:
1. Better attention kernels, especially for 38K-74K-token sequences.
2. Eliminating Q/K/V transpose and contiguous copies.
3. Fusing NVFP4 activation scaling, packing, GEMM, bias, and epilogues.
4. Replacing or tuning Comfy Kitchen GEMMs independently for SM100, SM120, and SM121.
5. CUDA graphs or persistent execution to reduce thousands of kernel launches per sample.
GB10 profiling at 1344x768/124 frames produced 37,810 packed tokens. Sage2
attention remains the parity baseline; native NHD layout was exact but did not
improve median path time, and Sol-Attn was faster but materially changed the
attention output. The first retained optimization routes H3 activation-scale
discovery through the parity-safe Vortex kernel when
`H3_NVFP4_SCALE_BACKEND=vortex`, while retaining Comfy Kitchen's packer and
GEMM. Representative blocks 0, 24, and 49 improved by `3.1%`, `8.8%`, and
`3.3%` respectively with identical output checksums. Details are recorded in
`benchmarks/gb10-37810-token-optimization-profile-seed440420.json`.
The expanded sampling profile confirms that the denoiser consumes effectively
all warmed-step latency. At block 24, Sage2 spends about `50.5%` in attention,
`29.3%` in NVFP4 projections, `12.6%` in modulation/gates/SwiGLU, `4.0%` in
layout materialization, and `3.8%` in norm/RoPE. Sol's sparse timing is a useful
performance bound, but not an accepted backend: its first speed-positive
settings differ substantially from Sage2, while fully dense Sol is `3.2x`
slower. See
`benchmarks/gb10-sampling-component-profile-1344x768-124f-seed440420.json`.
Validation and profiling sequence:
1. Use `tools/profile_h3_block.py` to measure one representative H3 block before writing kernels. Record QKV, RoPE/RMS, attention kernel, output projection, MLP fc1, activation, MLP fc2, modulation/gating, and total block time.

14
README.md
View file

@ -23,8 +23,6 @@ Implemented and validated:
- Opt-in EasyCache and H3-Cache experiments.
- Ragged Ulysses sequence parallelism and true NVFP4 tensor parallelism with
automatic 1/2/4/6/8-GPU launch tooling.
- Opt-in bit-exact Triton fusion for H3 segmented modulation and residual gates;
enabled by default in the validated Spark deployment.
The main remaining feature gap is full arbitrary Ref2VA, especially reference
video/audio, identity, and voice conditioning. Multi-GPU code is CPU- and
@ -150,12 +148,6 @@ read/write is available and NCCL selected `P2P/CUMEM`; topology varied between
`SYS` and `NODE` across RunPod allocations. See
`benchmarks/rtxpro6000-server-1v2-sdpa-scaling-seed440420.json`.
A matched one-GPU B200 SDPA run took `79.72s` at 1344x768/124 frames and
`257.86s` at 1344x768/243 frames. That is only `1.23x` and `1.21x` faster than
one RTX PRO 6000, while the measured sampling cost at RunPod rates was `2.64x`
and `2.69x` higher. See
`benchmarks/b200-vs-rtxpro6000-server-sdpa-1344x768-seed440420.json`.
Matched GB10 backend results and parity evidence are recorded in [`PLAN.md`](PLAN.md)
and [`PARITY.md`](PARITY.md). Standalone `tools/compare_*`, `tools/trace_*`,
`tools/inspect_*`, and `tools/patch_comfy_*` commands are diagnostic utilities,
@ -173,12 +165,6 @@ not runtime startup requirements.
- [`FLASH4.md`](FLASH4.md): FlashAttention-4 integration and benchmark.
- [`PARITY.md`](PARITY.md): direct-versus-Comfy evidence ledger.
- [`PLAN.md`](PLAN.md): historical investigation and future kernel plan.
- [`PERFORMANCE_ROADMAP.md`](PERFORMANCE_ROADMAP.md): measured bottlenecks,
architecture targets, quality gates, and the ordered optimization plan.
- [`VORTEX_RESEARCH_AGENDA.md`](VORTEX_RESEARCH_AGENDA.md): flagship research
thesis, novel systems contributions, evaluation targets, and project ranking.
- [`NVFP4_STREAMING_DESIGN.md`](NVFP4_STREAMING_DESIGN.md): measured GEMM
interface boundary and the exact producer-consumer kernel prototype sequence.
## Known Gaps

163
SAGE2_BLACKWELL_DESIGN.md
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@ -1,163 +0,0 @@
# Sage2 Blackwell Mainloop
## Decision
The adjacent NVFP4 producer fusions are complete. The next exact kernel
experiment is now a retune of SageAttention 2.2.0's existing classic SM89
mainloop. Do not replace the algorithm with UMMA, FP8 Q/K, or FP4 attention.
The canonical GB10 profile is dominated by the attention kernel:
- Complete block 24: 468.22 ms median.
- Sage2 NHD path: 260.02 ms median.
- SM89 attention mainloop: 238.81 ms median.
- Q/K quantization: 7.68 ms median.
- V quantization: 10.65 ms median.
- Remaining framework overhead: 2.87 ms estimated.
The fresh real block-24 decomposition supersedes those internal timings:
- Fused mainloop: 237.09 ms uninstrumented median.
- K mean/smoothing: 2.37 ms median.
- Q quantization: 3.80 ms median.
- K subtract-mean quantization: 3.83 ms median.
- V transpose/pad/permute: 5.08 ms median.
- V scale/FP8 quantization: 5.53 ms median.
- Manual decomposition versus public Sage2: byte-exact.
Q/K RMSNorm plus RoPE is 12.20 ms and is not the first target. NVFP4 ring
dispatch is also excluded because it failed the controlled block gate.
## Existing Contract
For the 37,810-token H3 shape, preserve these Sage2 inputs and outputs:
- Batch 1, 56 heads, head dimension 128, non-causal attention.
- Projection-strided BF16 NHD Q/K/V input.
- Per-warp INT8 Q with 128-row blocks and 32-row warp groups.
- Per-block INT8 K with 64-row blocks.
- FP8 V and the existing per-channel scale layout.
- Sage2's `fp32+fp16` instantaneous-buffer accumulation order.
- Contiguous BF16 NHD output with exact equality to Sage2 2.2.0.
The current mainloop is
`sageattention_sm89::qk_int8_sv_f8_accum_f16_fuse_v_scale_attn_inst_buf`.
It receives Q/K INT8 tensors, FP8 V, Q/K/V scales, and emits the final BF16
attention output.
## Rejected Shortcut
SageAttention's Hopper SM90 WGMMA source was compiled experimentally for
`sm_121a`. CUDA 13 ptxas rejects `wgmma.fence`, `wgmma.mma_async`,
`wgmma.commit_group`, and `wgmma.wait_group` for SM121, including both INT8 and
FP8 forms. A Hopper binary or source retarget is therefore not viable.
CUTLASS 4.6 SM120/121 exposes `tcgen05`/UMMA for F8/F6/F4 but not INT8. It
therefore cannot preserve Sage2's INT8 QK operation. Changing Q/K to FP8 or FP4
would define a different attention algorithm and require a quality gate rather
than exact parity.
## Scheduler Diagnosis
The full-counter capture reports 255 registers/thread and 32 KiB dynamic shared
memory for each 128-thread CTA. Registers limit residency to two CTAs, producing
`16.83%` achieved occupancy and only `0.46` eligible warps per scheduler. No
warp is eligible in `63.53%` of scheduler cycles. Fixed-latency dependency
stalls are `2.01` cycles and math-pipe throttle is `1.24` cycles out of the
`5.48` cycles between issued instructions.
The fused phase attribution is counter-based rather than separate wall time:
- INT8 QK uses `37.77%` of elapsed tensor-pipe capacity.
- FP8 PV uses `37.77%` of elapsed tensor-pipe capacity.
- Scalar FMA and ALU pipelines use `15.01%` and `8.81%`, covering scale,
online-softmax, conversion, normalization, and output work.
- Combined tensor activity is `75.54%`; the INT and FP sub-pipelines alternate,
so neither individually exceeds `37.77%`.
- Memory throughput is `31.61%`, L2 hit rate is `98.84%`, and the warm
off-chip request proxy is only `1.85 GB`. This is not a DRAM bottleneck.
- Shared accesses create `626,970,624` excessive wavefronts, `7.68%` of all
shared wavefronts.
- Real Q and KV tail CTAs each cost less than 1 ms.
## Completed P0
The source-identical classic `mma.sync` retune was completed without an accepted
variant. The exact three-CTA threshold is 168 registers/thread; 170 remains at
two CTAs. The 168-register cap causes `4.95 billion` local spill requests and
worsens no-eligible cycles from `63.13%` to `78.79%`. Narrowed scopes reduce
static spills from 44/44 to 12/12 bytes but improve real-input latency by only
`0.06%`. In-place score reuse, early K prefetch, and independent softmax-chain
interleaving are also neutral or slower.
The shared excess is produced by repeated V-staging `LDGSTS.128` instructions.
A 128-byte padded V layout leaves all `626,970,624` excessive wavefronts
unchanged and provides no latency gain. This counter is therefore not an
actionable layout target for the exact kernel.
The P0 gate was:
1. Adversarial short-shape comparison against the Sage2 mainloop.
2. Exact real block-24 attention output at 37,810 tokens.
3. Mainloop median below 220 ms before block integration.
4. Blocks 0, 24, and 49 exact after integration.
5. Alternating block benchmark must improve all three blocks before trajectory
validation.
Use the Blackwell SageAttention3/CUTLASS code only as a scheduler reference. Its
FP4 algorithm and output are not a correctness replacement for Sage2.
No variant exceeded the 3% mainloop gate, so block integration and deployment
were intentionally skipped. Detailed evidence is in
`benchmarks/gb10-sage2-p0-register-scheduler-analysis.json`.
## Completed P1 And P2
P1 fused strided-NHD Q/K RMSNorm, split-half RoPE, and Q INT8 quantization. It
was byte-exact, but complete-block gains were only `0.53-0.86%`, below the 1%
gate, so its runtime branch was removed.
P2 replaced Sage2's separate BF16 V transpose and FP8 quantization with an owned
three-stage direct-NHD producer. It emits byte-identical FP8 V and FP32 scales
for 13 boundary lengths. Canonical V preparation improves from `10.56 ms` to
`6.39 ms` (`39.48%`), but the `4.17 ms` saving is only `0.91%` of the complete
block and misses the `6.0 ms` isolated go threshold. No block integration or
trajectory validation was run. The validator-only implementation remains useful
for a future owned attention backend; production Sage2 remains unchanged.
These results close the remaining preparation-only Sage2 opportunities. The
next Sage-class optimization with plausible multi-percent block impact is a new
warp-specialized QK/PV mainloop or a quality-gated Blackwell-native attention
algorithm, not another launch-boundary fusion.
## Completed P3
P3 tested the smallest exact temporal QK/PV specialization. Warp pairs A and B
alternated INT8 QK plus online softmax against the other pair's prior-tile FP8
PV. Every warp retained its original query rows and private `RS`, `RS_f8`, `RO`,
`m`, and `d`; no numerical state crossed warp boundaries. The candidate is
compute-sanitizer clean and byte-exact across 13 short boundary cases and the
real block-24 output SHA.
The schedule does not produce a material latency gain. In a rotating 50-sample
comparison, baseline median is `245.44 ms` and the candidate is `245.20 ms`, a
`0.10%` improvement. It remains far above the `<220 ms` gate. Ptxas reports 254
registers/thread and 32/24-byte static store/load spills for the candidate,
versus 255 registers and 24/24-byte spills for the clean baseline build. NCU and
block integration were skipped because the latency gate failed.
This closes temporal warp separation as an exact Sage2 optimization on the
current SM89 instruction stream. A multi-percent attention gain now requires a
substantially new mainloop or a quality-gated Blackwell-native attention
algorithm rather than another exact schedule rearrangement.
## Successor Research
Vortex Exact Attention supersedes further source-identical Sage2 retuning. Its
Phase 0 contract imports this document and retained P0-P3 evidence without
claiming unrecoverable P0 source. Phase 1 evaluates only architectures that move
or partition `RS/RS_f8`, `m/d`, and `RO` ownership. The recommended VEA-B design
uses separate QK/softmax and PV/output warps around the still-supported exact
INT8 `mma.sync` arithmetic on SM121. No kernel or production dispatch exists;
projected latency ranges are not achieved results. See
`research/vortex_exact_attention/`.

6
TURBO.md
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@ -30,12 +30,6 @@ output = NVFP4_base(x) + strength * (alpha / rank) * B(A(x))
The BF16 branch receives the original activation. It does not receive the base checkpoint's `pre_quant_scale`-modified activation, and the LoRA delta is never merged into packed NVFP4 weights. Fused QKV uses rank/alpha 384; the other released projections use rank/alpha 128.
Active LoRA intentionally uses the materialized projection fallback. Emitting
the exact BF16 LoRA input while the NVFP4 modulation and SwiGLU producers pack
was bit-exact, but slowed an isolated canonical Turbo-4 trajectory by `3.08%`.
The rejected result is recorded in
`benchmarks/gb10-nvfp4-lora-producer-fusion-turbo4-isolated.json`.
Turbo sampling maintains independent native video and audio states. The 4-step and 8-step variants use their own shifted sigma grids and positive data-ward training-Euler updates. The original beta/RES sampler remains unchanged when Turbo is disabled.
## Hot API

185
VORTEX_RESEARCH_AGENDA.md
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@ -1,185 +0,0 @@
# Vortex Research Agenda
## Flagship Research Project
**Vortex: Reference-Exact, Communication-Avoiding Video Diffusion on Commodity PCIe GPUs**
The core research question:
> Can a large multimodal video diffusion model achieve near-NVLink scaling on
> ordinary PCIe hardware while preserving reference-exact output?
The existing `86.1%` two-GPU efficiency is the starting evidence, not the final
contribution.
## Novel Architecture
Build an end-to-end H3 block where:
- NVFP4 QKV projections write directly into rank-destined communication buffers.
- Q, K, and V are never separately materialized or repacked.
- Ulysses communication begins at tile granularity while later projection tiles
are still computing.
- Video, audio, text, and conditioning tokens use different sharding policies.
- Small conditioning segments are replicated when replication is cheaper than
communication.
- Received attention output writes directly into the output-projection layout.
- Reference BF16 rounding boundaries are preserved exactly.
- The scheduler automatically accounts for PIX, PXB, PHB, NODE, and SYS topology.
The target pipeline is:
```text
NVFP4 projection
|
v
rank-destined QKV tiles
|
v overlapping
PCIe all-to-all
|
v overlapping
attention
|
v
output projection layout
```
There is no intermediate QKV pack, full synchronization point, or redundant
memory round trip.
Communication and computation overlap has already been explored by systems such
as Ulysses Unbound and topology-aware systems such as SwiftFusion. The
contribution therefore cannot simply be "we overlapped an all-to-all."
The novel combination is:
- Direct NVFP4 GEMM-to-collective dataflow.
- Ragged multimodal sequence parallelism.
- Segment-aware replication and sharding.
- Reference-exact numerical behavior.
- Automatic PCIe topology adaptation.
- Scaling across inexpensive non-NVLink hardware.
That combination appears meaningfully ahead of public H3 implementations.
## Rounding-Boundary-Aware Exact Fusion
Create a compiler or kernel-generation framework that understands where the
original model performs BF16 rounding.
Ordinary fusion can silently change output because fused multiply-add performs
one rounding where separate operations perform two. NVIDIA documents this
numerical distinction in its CUDA floating-point guidance.
The system would:
- Trace the reference H3 graph.
- Mark mandatory numerical materialization boundaries.
- Fuse everything between safe boundaries.
- Generate Triton or CUDA kernels.
- Prove equivalence with adversarial and randomized testing.
- Preserve bitwise behavior across SM100, SM120, and SM121 where possible.
Apply it to:
- AdaLN modulation.
- Residual gates.
- SwiGLU.
- QK normalization and RoPE.
- NVFP4 scaling and packing.
- GEMM epilogues.
This could be a broader contribution than Vortex itself. It would answer:
> How much of a mixed-precision transformer can be fused without altering its
> numerical program?
That is a serious systems and numerical-computing paper.
## Trajectory-Bounded Sparse Attention
This is the highest-risk project.
The Sol results show why simple threshold sparsity is not enough:
- It becomes fast at higher thresholds.
- Attention-level relative error rises to roughly `0.5-0.6`.
- Local attention error does not reveal what happens to the final video.
Instead of using one global threshold, allocate an error budget across:
- Denoising timestep.
- Transformer block.
- Attention head.
- Video, audio, text, and conditioning segments.
- Spatial and temporal regions.
The runtime would choose dense or sparse attention dynamically, with exact
fallback when its predicted error exceeds the remaining trajectory budget.
Existing research already covers distributed sparse attention, including DSA,
and feature reuse such as FasterCache. The potential Vortex contribution is
different:
> Optimize sparsity against final multimodal trajectory error, not isolated
> attention-tensor error.
That requires proper evaluation of image quality, temporal consistency, audio
quality, lip synchronization, and prompt adherence.
## Practical Ranking
| Research direction | Novelty | Technical risk | Commercial value | Recommendation |
| --- | --- | --- | --- | --- |
| PCIe-native ragged Ulysses | Very high | Medium | Exceptional | First |
| Rounding-aware exact fusion | Very high | Medium | Exceptional | Build alongside |
| Trajectory-bounded sparsity | Very high | Very high | Potentially exceptional | Later |
| NVFP4 block superkernel | Medium-high | Medium | Very high | Core component |
| Topology-autonomous planner | Medium | Low-medium | High | Supporting work |
| Conventional caching | Medium-low | Medium | High | Only with a novel error guarantee |
## Landmark Result
A compelling target is:
| Scale | Target efficiency | Interconnect |
| --- | ---: | --- |
| 2 GPUs | Above `90%` | PCIe, no NVLink |
| 4 GPUs | Above `80%` | PCIe |
| 8 GPUs | Above `70%` | PCIe or cross-NUMA |
| Output | Reference-exact or formally bounded | All scales |
| Portability | SM100, SM120, SM121 | Same runtime |
Also measure:
- End-to-end latency, not sampling alone.
- Exposed communication time.
- Bytes transferred per block.
- HBM traffic and achieved bandwidth.
- Tensor-core utilization.
- Cost per generated second.
- Energy per generated second.
- PIX/NODE/PHB/SYS topology sensitivity.
- Comparison against SGLang, xDiT, and LightX2V.
## Recommendation
Do not lead with sparse attention yet. Lead with:
> Reference-exact, communication-avoiding ragged Ulysses with direct NVFP4
> projection-to-collective dataflow.
The first fused modulation kernel establishes the exact-fusion infrastructure.
Use that infrastructure next to build the direct QKV-to-Ulysses path.
The measured single-GPU implementation order is direct QKV-to-attention layout,
direct attention-to-output-projection layout, streamed NVFP4 scale/pack/GEMM,
and exact residual-gate epilogues. This order attacks the measured `105.83 ms`
layout boundary first while preserving the larger projection-to-collective
architecture as the distributed destination.
If strong four-GPU and eight-GPU scaling over PCIe can be demonstrated while
retaining exact output, this stops being merely an excellent H3 runtime. It
becomes credible new research into how large generative models should be
executed without proprietary high-bandwidth interconnects.

107
benchmarks/b200-vs-rtxpro6000-server-sdpa-1344x768-seed440420.json
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@ -1,107 +0,0 @@
{
"device": "NVIDIA B200",
"comparison_device": "NVIDIA RTX PRO 6000 Blackwell Server Edition",
"attention": "sdpa",
"mode": "tensor",
"world_size": 1,
"steps": 12,
"seed": 440420,
"torch": "2.9.1+cu130",
"hourly_usd": {
"b200": 6.79,
"rtx_pro_6000": 2.09
},
"b200_host": {
"data_center": "US-NC-2",
"driver": "580.105.08",
"memory_mib": 183359,
"power_limit_w": 1000
},
"results": [
{
"resolution": [
1344,
768
],
"frames": 124,
"video_seconds_at_24fps": 5.166666666666667,
"b200": {
"model_load_seconds": 11.831760542932898,
"conditioning_seconds": 45.36778333503753,
"sampling_seconds": 79.72125827614218,
"sampling_cost_usd": 0.15036315102639039,
"sampling_peak_allocated_bytes": 17246854656,
"checksums": [
-83553.09375,
-397.89813232421875
],
"console_step_seconds_rounded": [
6.4,
6.1,
6.1,
6.1,
6.1,
6.1,
6.1,
6.1,
6.1,
6.1,
6.1,
6.1
]
},
"rtx_pro_6000": {
"sampling_seconds": 97.94385590963066,
"sampling_cost_usd": 0.05686184968086891
},
"b200_speedup": 1.2285789013812125,
"b200_sampling_cost_ratio": 2.6443591242685138
},
{
"resolution": [
1344,
768
],
"frames": 243,
"video_seconds_at_24fps": 10.125,
"b200": {
"model_load_seconds": 10.712746233213693,
"conditioning_seconds": 38.57332478091121,
"sampling_seconds": 257.8619639207609,
"sampling_cost_usd": 0.48635631528387957,
"sampling_peak_allocated_bytes": 22955644416,
"checksums": [
41606.85546875,
629.4112548828125
],
"console_step_seconds_rounded": [
21.4,
21.1,
21.1,
21.1,
21.0,
21.0,
21.0,
21.0,
21.0,
21.0,
21.0,
21.0
]
},
"rtx_pro_6000": {
"sampling_seconds": 311.01632468774915,
"sampling_cost_usd": 0.18056225516594326
},
"b200_speedup": 1.2061349411862938,
"b200_sampling_cost_ratio": 2.6935657999890426
}
],
"cost_scope": "Sampling wall time only. Model/Qwen loading, text conditioning, VAE decode, media encoding, muxing, and pod startup are excluded.",
"notes": [
"The 124-frame run preceded the 243-frame run on the same host.",
"Both successful runs followed one pre-sampling dependency failure, so host and network-volume file caches were warm.",
"Console step durations are rounded to one decimal place; sampling_seconds is the authoritative synchronized benchmark timer.",
"The RTX PRO 6000 measurements are copied from rtxpro6000-server-1v2-sdpa-scaling-seed440420.json."
]
}

75
benchmarks/gb10-37810-token-optimization-profile-seed440420.json
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@ -1,75 +0,0 @@
{
"device": "NVIDIA GB10",
"compute_capability": "SM121",
"torch": "2.9.1+cu130",
"resolution": [
1344,
768
],
"frames": 124,
"packed_tokens": 37810,
"seed": 440420,
"attention": "sage2",
"representative_block_results": [
{
"block": 0,
"comfy_scale_p50_seconds": 0.5251280819647945,
"vortex_scale_p50_seconds": 0.5088961640140042,
"speedup": 1.031896326006387,
"latency_reduction": 0.0309103978786619,
"checksum": -8279139.0
},
{
"block": 24,
"comfy_scale_p50_seconds": 0.5646577654988505,
"vortex_scale_p50_seconds": 0.5149167295021471,
"speedup": 1.0966001552227602,
"latency_reduction": 0.08809059050619694,
"checksum": 89071408.0
},
{
"block": 49,
"comfy_scale_p50_seconds": 0.524194426019676,
"vortex_scale_p50_seconds": 0.5067900969879702,
"speedup": 1.034342283196033,
"latency_reduction": 0.03320204902570367,
"checksum": -40617144320.0
}
],
"block_24_quantization_p50_milliseconds": {
"attn_qkv_proj": {
"comfy": 9.078,
"vortex": 3.908
},
"attn_out_proj": {
"comfy": 10.035,
"vortex": 5.151
},
"mlp_fc1": {
"comfy": 7.27,
"vortex": 5.182
},
"mlp_fc2": {
"comfy": 19.187,
"vortex": 10.163
}
},
"attention_findings": [
"Sage2 was substantially faster than PyTorch SDPA, forced cuDNN SDPA, and FlashAttention-4 at 37,810 tokens.",
"Sage2 NHD produced an exact output but did not materially improve median total path time and had worse tail latency.",
"Strict Sol-Attn reached about 157 ms kernel time versus about 260 ms for Sage2, but its output differed materially from Sage2 and is not a correctness-preserving replacement.",
"Explicit Sage2 kernel variants did not provide an exact speed improvement over the Sage2 dispatcher."
],
"validation": {
"linear_reference_diff": "zero for all four Vortex-scale plus Comfy-pack H3 linears",
"block_checksums": "identical for Comfy and Vortex paths at blocks 0, 24, and 49",
"remote_contracts": "28 passed",
"full_model_smoke": "not run: the deployed image predates the distributed runner; direct preview did not produce an artifact while resident services remained active"
},
"notes": [
"The optimization changes activation-scale discovery only; Comfy Kitchen still packs activations and executes scaled_mm_nvfp4.",
"The default H3_NVFP4_SCALE_BACKEND=torch path is unchanged.",
"The native Vortex packer is not enabled because the attention output projection failed parity in this profile.",
"Resident H3 and Qwen services remained running during profiling, so medians are preferred over means and tail latency requires an isolated rerun."
]
}

22
benchmarks/gb10-component2-layout-hnd-2step.json
View file

@ -1,22 +0,0 @@
{
"device": "NVIDIA GB10",
"torch": "2.9.1+cu130",
"attention": "sage2",
"resolution": [
1344,
768
],
"frames": 124,
"steps": 2,
"seed": 440420,
"text_tokens": 100,
"elapsed_seconds": 52.49690314201871,
"stage_trace": [],
"checksums": [
-276716.375,
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],
"peak_allocated_bytes": 18867826176,
"peak_reserved_bytes": 21846032384,
"measurement_policy": "uninstrumented sampling wall time"
}

22
benchmarks/gb10-component2-layout-strided-nhd-12step.json
View file

@ -1,22 +0,0 @@
{
"device": "NVIDIA GB10",
"torch": "2.9.1+cu130",
"attention": "sage2",
"resolution": [
1344,
768
],
"frames": 124,
"steps": 12,
"seed": 440420,
"text_tokens": 100,
"elapsed_seconds": 290.2269145210157,
"stage_trace": [],
"checksums": [
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],
"peak_allocated_bytes": 17680283648,
"peak_reserved_bytes": 19809697792,
"measurement_policy": "uninstrumented sampling wall time"
}

22
benchmarks/gb10-component2-layout-strided-nhd-2step.json
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@ -1,22 +0,0 @@
{
"device": "NVIDIA GB10",
"torch": "2.9.1+cu130",
"attention": "sage2",
"resolution": [
1344,
768
],
"frames": 124,
"steps": 2,
"seed": 440420,
"text_tokens": 100,
"elapsed_seconds": 50.95522483601235,
"stage_trace": [],
"checksums": [
-276716.375,
727.1075439453125
],
"peak_allocated_bytes": 17681987584,
"peak_reserved_bytes": 19809697792,
"measurement_policy": "uninstrumented sampling wall time"
}

69
benchmarks/gb10-component2-nsys-summary-1344x768-124f-seed440420.json
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@ -1,69 +0,0 @@
{
"device": "NVIDIA GB10",
"compute_capability": "SM121",
"workload": {
"resolution": [1344, 768],
"frames": 124,
"packed_tokens": 37810,
"block": 24,
"attention": "sage2",
"seed": 440420
},
"capture": {
"tool": "Nsight Systems 2025.3.2",
"scope": "one warmed H3 block between cudaProfilerStart and cudaProfilerStop",
"fused_elementwise": true,
"runtime_kernel_launches": 53,
"cudaLaunchKernel_calls": 45,
"cuLaunchKernelEx_calls": 8
},
"component1_residual": {
"modulation_launches": 2,
"modulation_total_ms": 9.5432,
"gate_add_launches": 2,
"gate_add_total_ms": 10.936032,
"unfused_modulation_gate_or_add_launches": 0,
"conclusion": "The four fused kernels perform substantial tensor traffic and are not launch-bound. Eliminate that traffic only at adjacent NVFP4 boundaries."
},
"nvfp4": {
"launches": 32,
"gemm_launches": 4,
"gemm_total_ms": 162.339136,
"activation_pack_launches": 4,
"activation_pack_total_ms": 13.121248,
"absmax_partial_launches": 4,
"absmax_partial_total_ms": 10.767616,
"scale_finalize_launches": 4,
"scale_finalize_total_ms": 0.013536,
"block_scale_zero_launches": 4,
"block_scale_zero_total_ms": 0.292992,
"small_scale_conversion_launches": 12,
"intermediate_materialization_bytes_across_four_projections": 7732981760,
"conclusion": "Scale discovery, activation packing, buffer initialization, GEMM, and output allocation remain separate. The global scale dependency requires an explicit synchronization design in any exact fused implementation."
},
"other_boundaries": {
"qkv_and_attention_layout_copy_launches": 4,
"qkv_and_attention_layout_copy_total_ms": 105.83168,
"swiglu_silu_total_ms": 9.390784,
"swiglu_multiply_total_ms": 14.38736
},
"native_pack_validation": {
"initial_finding": "The previous width-specific block-scale swizzle failed for the 7168-feature attention output projection while QDATA remained exact.",
"fix": "Replaced width-specific indexing with the general 128-row by 4-scale-column tiled offset.",
"validated_feature_widths": [5376, 7168, 14336],
"qdata_difference_count": 0,
"block_scale_difference_count": 0,
"linear_output_max_abs_difference": 0.0,
"deployment_decision": "Do not enable the standalone native packer for performance; it is not consistently faster than Comfy packing. Use it as exact infrastructure for the fused prototype."
},
"validation": {
"deployed_tests": "33 passed",
"new_regression": "Comfy packed QDATA and block-scale identity at feature widths 5376, 7168, and 14336"
},
"source_artifacts": [
"benchmarks/gb10-nvfp4-component2-profile-1344x768-124f-seed440420.json",
"benchmarks/gb10-nvfp4-pack-parity-component2-fixed-1344x768-124f-seed440420.json",
"benchmarks/gb10-nvfp4-native-fixed-component2-1344x768-124f-seed440420.json",
"benchmarks/gb10-fused-block-residual-profile-component2-1344x768-124f-seed440420.json"
]
}

88
benchmarks/gb10-cute-nvfp4-conversion-contract.json
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@ -1,88 +0,0 @@
{
"device": "NVIDIA GB10",
"cutlass_dsl": "4.6.2",
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benchmarks/gb10-cute-p0-attn-out-128rows.json
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85
benchmarks/gb10-cute-p0-attn-qkv-128rows-alpha.json
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83
benchmarks/gb10-cute-p0-attn-qkv-128rows.json
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62
benchmarks/gb10-cute-p0-h3-summary.json
View file

@ -1,62 +0,0 @@
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85
benchmarks/gb10-cute-p0-mlp-fc1-128rows-alpha.json
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83
benchmarks/gb10-cute-p0-mlp-fc1-128rows.json
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85
benchmarks/gb10-cute-p0-mlp-fc2-128rows-alpha.json
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83
benchmarks/gb10-cute-p0-mlp-fc2-128rows.json
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46
benchmarks/gb10-cute-p1-real-tiles-attn-out.json
View file

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benchmarks/gb10-cute-p1-stream-a-attn-out-128rows-alpha.json
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benchmarks/gb10-cute-p1-stream-a-attn-qkv-128rows-alpha.json
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86
benchmarks/gb10-cute-p1-stream-a-mlp-fc1-128rows-alpha.json
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54
benchmarks/gb10-cute-p1-stream-a-summary.json
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50
benchmarks/gb10-cute-p1-stream-a-timing-summary.json
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98
benchmarks/gb10-cute-p1-timing-p0-attn-out.json
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benchmarks/gb10-cute-p1-timing-p0-attn-qkv.json
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98
benchmarks/gb10-cute-p1-timing-p0-mlp-fc1.json
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benchmarks/gb10-cute-p1-timing-stream-attn-out.json
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benchmarks/gb10-cute-p1-timing-stream-attn-qkv.json
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benchmarks/gb10-cute-p1-timing-stream-mlp-fc1.json
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benchmarks/gb10-cute-p2-ring-attn-out.json
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benchmarks/gb10-cute-p2-ring-attn-qkv.json
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78
benchmarks/gb10-cute-p2-ring-capacity-attn-out-1024.json
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72
benchmarks/gb10-cute-p2-ring-capacity-attn-out-128.json
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78
benchmarks/gb10-cute-p2-ring-capacity-attn-out-2048.json
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78
benchmarks/gb10-cute-p2-ring-capacity-attn-out-4096.json
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78
benchmarks/gb10-cute-p2-ring-capacity-attn-out-512.json
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78
benchmarks/gb10-cute-p2-ring-capacity-attn-qkv-2048.json
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78
benchmarks/gb10-cute-p2-ring-capacity-mlp-fc1-2048.json
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58
benchmarks/gb10-cute-p2-ring-capacity-summary.json
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@ -1,58 +0,0 @@
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205
benchmarks/gb10-cute-p2-ring-full-block0-attn-out.json
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@ -1,205 +0,0 @@
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205
benchmarks/gb10-cute-p2-ring-full-block0-fc1.json
View file

@ -1,205 +0,0 @@
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205
benchmarks/gb10-cute-p2-ring-full-block0-qkv.json
View file

@ -1,205 +0,0 @@
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330
benchmarks/gb10-cute-p2-ring-full-block24-attn-out-1024.json
View file

@ -1,330 +0,0 @@
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205
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205
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205
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205
benchmarks/gb10-cute-p2-ring-full-block49-qkv.json
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@ -1,205 +0,0 @@
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46
benchmarks/gb10-cute-p2-ring-full-projection-summary.json
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@ -1,46 +0,0 @@
{
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67
benchmarks/gb10-cute-p2-ring-mlp-fc1.json
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@ -1,67 +0,0 @@
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49
benchmarks/gb10-cute-p2-ring-summary.json
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@ -1,49 +0,0 @@
{
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27
benchmarks/gb10-cute-qkv-block0-alternating.json
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@ -1,27 +0,0 @@
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852
benchmarks/gb10-cute-qkv-block0-baseline.json
View file

@ -1,852 +0,0 @@
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852
benchmarks/gb10-cute-qkv-block0-ring.json
View file

@ -1,852 +0,0 @@
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27
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852
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27
benchmarks/gb10-cute-qkv-block24-capacity3072-alternating.json
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27
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852
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27
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852
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852
benchmarks/gb10-cute-qkv-block49-ring.json
View file

@ -1,852 +0,0 @@
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38
benchmarks/gb10-cute-qkv-runtime-block-gate-summary.json
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42
benchmarks/gb10-cute-qkv-runtime-block24-2048.json
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"improvement_percent": 12.913285441989618
}

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benchmarks/gb10-cute-qkv-runtime-block24-full.json
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{
"device": "NVIDIA GB10",
"metadata": {
"width": 1344,
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"ring_ms": 31.741008758544922,
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}

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benchmarks/gb10-four-gemm-nvfp4-roofline.json
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{
"status": "complete",
"device": "NVIDIA GB10",
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"workload": {
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"frames": 124,
"tokens": 37810,
"block": 24,
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},
"method": {
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"l2_traffic": "Nsight Compute lts__t_bytes.sum with cache control disabled",
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"practical_compute_ceiling_tflops_per_s": 321.455895,
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},
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{
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},
{
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}
],
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"do_not_target_first": ["attention_qkv", "attention_output", "mlp_fc1"],
"reason": "QKV, attention output, and FC1 cluster at 315-321 dense-equivalent TFLOP/s and lie above the practical ridge point. FC2 uses stream-K, reaches only 106 TFLOP/s, and generates 12.16 GB of off-chip request traffic, 16.1x its ideal unique bytes.",
"next_experiment": "Benchmark an exact FC2 schedule that reduces K-split/stream-K rereads and reuses the fused SwiGLU-produced activation tiles. Require bit-exact BF16 output and at least 3% complete-block improvement before integration."
},
"source_artifacts": [
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"benchmarks/gb10-fully-fused-block24-fresh-l2-misses-warm.csv",
"benchmarks/gb10-fully-fused-fresh-nsight-summary.json"
]
}

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