73 lines
2.9 KiB
JSON
73 lines
2.9 KiB
JSON
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{
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"device": "NVIDIA GB10",
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"workload": "real H3 block 24, 37810 tokens, 56 heads, head dimension 128",
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"parity": {
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"manual_preparation_and_mainloop_vs_public_sage2_equal": true,
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"max_abs": 0.0,
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"mean_abs": 0.0
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},
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"uninstrumented_phase_medians_ms": {
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"k_mean_and_smoothing": 2.365136,
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"q_int8_quantization": 3.799392,
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"k_int8_subtract_mean_quantization": 3.825936,
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"v_transpose_pad_permute": 5.081152,
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"v_scale_fp8_quantization": 5.531616,
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"fused_mainloop": 237.089394
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},
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"ncu_mainloop": {
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"profiler_perturbed_duration_ms": 258.918464,
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"registers_per_thread": 255,
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"dynamic_shared_memory_bytes_per_cta": 32768,
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"threads_per_cta": 128,
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"grid_ctas": 16576,
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"theoretical_occupancy_percent": 16.67,
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"achieved_occupancy_percent": 16.83,
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"active_warps_per_sm": 8.08,
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"compute_throughput_percent": 75.54,
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"memory_throughput_percent": 31.61,
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"tensor_int_elapsed_cycles_percent": 37.77,
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"tensor_fp_elapsed_cycles_percent": 37.77,
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"fma_elapsed_cycles_percent": 15.01,
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"alu_elapsed_cycles_percent": 8.81,
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"scheduler_cycles_no_eligible_warp_percent": 63.53,
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"eligible_warps_per_scheduler": 0.46,
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"issued_warps_per_scheduler": 0.36,
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"warp_cycles_per_issued_instruction": 5.48,
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"warp_stall_cycles_per_instruction": {
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"wait_fixed_latency_dependency": 2.01,
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"math_pipe_throttle": 1.24,
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"not_selected": 0.26,
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"short_scoreboard": 0.25,
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"barrier": 0.19,
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"dispatch": 0.16,
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"long_scoreboard": 0.13,
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"mio_throttle": 0.12
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},
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"l2_request_sectors": 5046921579,
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"l2_request_bytes": 161501490528,
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"l2_hit_rate_percent": 98.84,
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"l2_miss_sectors": 57882308,
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"off_chip_request_proxy_bytes": 1852233856,
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"shared_wavefronts": 8161078676,
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"excess_shared_wavefronts": 626970624,
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"excess_shared_wavefront_percent": 7.68,
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"local_spilling_requests": 1458688
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},
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"tail_study_ms": {
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"q_37760_aligned": 239.229565,
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"q_37761_one_row_tail": 239.632672,
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"q_37810_real_tail": 239.999844,
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"kv_37760_aligned": 239.823065,
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"kv_37761_one_row_tail": 240.594522,
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"kv_37810_real_tail": 240.623859
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},
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"diagnosis": [
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"The mainloop is compute/scheduler limited, not off-chip-bandwidth limited.",
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"INT8 QK and FP8 PV each consume 37.77% of elapsed tensor-pipe capacity; their sum explains the 75.54% aggregate tensor activity.",
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"The 255-register footprint limits occupancy to two CTAs and eight warps per SM, leaving no eligible warp in 63.53% of scheduler cycles.",
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"Fixed-latency dependencies and tensor math-pipe throttling dominate stalls; global-memory scoreboards are secondary.",
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"Tail CTAs add less than 1 ms and are not the primary optimization target.",
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"Shared-memory bank conflicts add 7.68% excessive wavefronts and are the safest secondary target after scheduling/register experiments."
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]
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}
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